mga_vid.c

来自「linux下的MPEG1」· C语言 代码 · 共 1,568 行 · 第 1/3 页

	     */		    ;
	break;

    case IMGFMT_YUY2:
	cregs.c2ctl = 1         // CRTC2 enabled
	    + (1<<1)	// external clock
	    + (0<<2)	// external clock
	    + (1<<3)	// pixel clock enable - not needed ???
	    + (0<<4)	// high priority req - acc to spec
	    + (1<<5)	// high priority req
	    + (0<<6)	// high priority req
	    // 7 reserved
	    + (1<<8)	// high priority req max
	    + (0<<9)	// high priority req max
	    + (0<<10)	// high priority req max
	    // 11-19 reserved
	    + (0<<20)   // CRTC1 to DAC
	    + (1<<21)   // 422 mode
	    + (0<<22)   // 422 mode
	    + (1<<23)   // 422 mode
	    + (0<<24)   // single chroma line for 420 mode - need to be corrected
	    + (0<<25)   /*/ interlace mode - need to be corrected*/
	    + (0<<26)   // field legth polariry
	    + (0<<27)   // field identification polariry
	    + (1<<28)   // VIDRST detection mode
	    + (0<<29)   // VIDRST detection mode
	    + (1<<30)   // Horizontal counter preload
	    + (1<<31)   // Vertical counter preload
	    ;
	cregs.c2datactl = 1         // disable dither - propably not needed, we are already in YUV mode
	    + (1<<1)	// Y filter enable
	    + (1<<2)	// CbCr filter enable
	    + (1<<3)	// subpicture enable (enabled)
	    + (0<<4)	// NTSC enable (disabled - PAL)
	    + (0<<5)	// C2 static subpicture enable (disabled)
	    + (0<<6)	// C2 subpicture offset division (disabled)
	    + (0<<7)	// 422 subformat selection !
	    /*		    + (0<<8)	// 15 bpp high alpha
	     + (0<<9)	// 15 bpp high alpha
	     + (0<<10)	// 15 bpp high alpha
	     + (0<<11)	// 15 bpp high alpha
	     + (0<<12)	// 15 bpp high alpha
	     + (0<<13)	// 15 bpp high alpha
	     + (0<<14)	// 15 bpp high alpha
	     + (0<<15)	// 15 bpp high alpha
	     + (0<<16)	// 15 bpp low alpha
	     + (0<<17)	// 15 bpp low alpha
	     + (0<<18)	// 15 bpp low alpha
	     + (0<<19)	// 15 bpp low alpha
	     + (0<<20)	// 15 bpp low alpha
	     + (0<<21)	// 15 bpp low alpha
	     + (0<<22)	// 15 bpp low alpha
	     + (0<<23)	// 15 bpp low alpha
	     + (0<<24)	// static subpicture key
	     + (0<<25)	// static subpicture key
	     + (0<<26)	// static subpicture key
	     + (0<<27)	// static subpicture key
	     + (0<<28)	// static subpicture key
	     */			;
	break;

    case IMGFMT_UYVY:
	cregs.c2ctl = 1         // CRTC2 enabled
	    + (1<<1)	// external clock
	    + (0<<2)	// external clock
	    + (1<<3)	// pixel clock enable - not needed ???
	    + (0<<4)	// high priority req
	    + (1<<5)	// high priority req
	    + (0<<6)	// high priority req
	    + (1<<8)	// high priority req max
	    + (0<<9)	// high priority req max
	    + (0<<10)	// high priority req max
	    + (0<<20)   // CRTC1 to DAC
	    + (1<<21)   // 422 mode
	    + (0<<22)   // 422 mode
	    + (1<<23)   // 422 mode
	    + (1<<24)   // single chroma line for 420 mode - need to be corrected
	    + (1<<25)   /*/ interlace mode - need to be corrected*/
	    + (0<<26)   // field legth polariry
	    + (0<<27)   // field identification polariry
	    + (1<<28)   // VIDRST detection mode
	    + (0<<29)   // VIDRST detection mode
	    + (1<<30)   // Horizontal counter preload
	    + (1<<31)   // Vertical counter preload
	    ;
	cregs.c2datactl = 0         // enable dither - propably not needed, we are already in YUV mode
	    + (1<<1)	// Y filter enable
	    + (1<<2)	// CbCr filter enable
	    + (1<<3)	// subpicture enable (enabled)
	    + (0<<4)	// NTSC enable (disabled - PAL)
	    + (0<<5)	// C2 static subpicture enable (disabled)
	    + (0<<6)	// C2 subpicture offset division (disabled)
	    + (1<<7)	// 422 subformat selection !
	    /*		    + (0<<8)	// 15 bpp high alpha
	     + (0<<9)	// 15 bpp high alpha
	     + (0<<10)	// 15 bpp high alpha
	     + (0<<11)	// 15 bpp high alpha
	     + (0<<12)	// 15 bpp high alpha
	     + (0<<13)	// 15 bpp high alpha
	     + (0<<14)	// 15 bpp high alpha
	     + (0<<15)	// 15 bpp high alpha
	     + (0<<16)	// 15 bpp low alpha
	     + (0<<17)	// 15 bpp low alpha
	     + (0<<18)	// 15 bpp low alpha
	     + (0<<19)	// 15 bpp low alpha
	     + (0<<20)	// 15 bpp low alpha
	     + (0<<21)	// 15 bpp low alpha
	     + (0<<22)	// 15 bpp low alpha
	     + (0<<23)	// 15 bpp low alpha
	     + (0<<24)	// static subpicture key
	     + (0<<25)	// static subpicture key
	     + (0<<26)	// static subpicture key
	     + (0<<27)	// static subpicture key
	     + (0<<28)	// static subpicture key
	     */		    ;
	break;
    }

    cregs.c2hparam=((hdispend - 8) << 16) | (htotal - 8);
    cregs.c2hsync=((hsyncend - 8) << 16) | (hsyncstart - 8);

    cregs.c2misc=0	// CRTCV2 656 togg f0
	+(0<<1) // CRTCV2 656 togg f0
	+(0<<2) // CRTCV2 656 togg f0
	+(0<<4) // CRTCV2 656 togg f1
	+(0<<5) // CRTCV2 656 togg f1
	+(0<<6) // CRTCV2 656 togg f1
	+(0<<8) // Hsync active high
	+(0<<9) // Vsync active high
	// 16-27 c2vlinecomp - nevim co tam dat
	;
    cregs.c2offset=(regs.bespitch << 1);

    cregs.c2pl2startadd0=regs.besa1corg;
    //cregs.c2pl2startadd1=regs.besa2corg;
    cregs.c2pl3startadd0=regs.besa1c3org;
    //cregs.c2pl3startadd1=regs.besa2c3org;

    cregs.c2preload=(vsyncstart << 16) | (hsyncstart); // from

    memset(config->dga_addr + config->offsets[config->num_frames], 0, config->frame_size); // clean spic area
    cregs.c2spicstartadd0=(uint32_t) mga_src_base + baseadrofs + config->num_frames*config->frame_size;
    //cregs.c2spicstartadd1=0; // not used

    cregs.c2startadd0=regs.besa1org;
    //cregs.c2startadd1=regs.besa2org;

    cregs.c2subpiclut=0; //not used

    cregs.c2vparam=((vdispend - 1) << 16) | (vtotal - 1);
    cregs.c2vsync=((vsyncend - 1) << 16) | (vsyncstart - 1);
#endif /* CRTC2 */

    mga_vid_write_regs(0);
    return(0);
}

int VIDIX_NAME(vixPlaybackOn)(void)
{
    if (mga_verbose) printf(MGA_MSG" playback on\n");

    vid_src_ready = 1;
    if(vid_overlay_on)
    {
	regs.besctl |= 1;
	mga_vid_write_regs(0);
    }
#ifdef MGA_ALLOW_IRQ
    if (mga_irq != -1)
	enable_irq();
#endif
    mga_next_frame=0;

    return(0);
}

int VIDIX_NAME(vixPlaybackOff)(void)
{
    if (mga_verbose) printf(MGA_MSG" playback off\n");

    vid_src_ready = 0;
#ifdef MGA_ALLOW_IRQ
    if (mga_irq != -1)
	disable_irq();
#endif
    regs.besctl &= ~1;
    regs.besglobctl &= ~(1<<6); /* UYVY format selected */
    mga_vid_write_regs(0);

    return(0);
}

int VIDIX_NAME(vixProbe)(int verbose,int force)
{
    pciinfo_t lst[MAX_PCI_DEVICES];
    unsigned int i, num_pci;
    int err;

    if (verbose) printf(MGA_MSG" probe\n");

    mga_verbose = verbose;

    is_g400 = -1;

    err = pci_scan(lst, &num_pci);
    if (err)
    {
	printf(MGA_MSG" Error occured during pci scan: %s\n", strerror(err));
	return(err);
    }

    if (mga_verbose)
	printf(MGA_MSG" found %d pci devices\n", num_pci);

    for (i = 0; i < num_pci; i++)
    {
	if (mga_verbose > 1)
	    printf(MGA_MSG" pci[%d] vendor: %d device: %d\n",
		   i, lst[i].vendor, lst[i].device);
	if (lst[i].vendor == VENDOR_MATROX)
	{
	    switch(lst[i].device)
	    {
	    case DEVICE_MATROX_MGA_G550_AGP:
		printf(MGA_MSG" Found MGA G550\n");
		is_g400 = 1;
		goto card_found;
	    case DEVICE_MATROX_MGA_G400_AGP:
		printf(MGA_MSG" Found MGA G400/G450\n");
		is_g400 = 1;
		goto card_found;
#ifndef CRTC2
	    case DEVICE_MATROX_MGA_G200_AGP:
		printf(MGA_MSG" Found MGA G200 AGP\n");
		is_g400 = 0;
		goto card_found;
	    case DEVICE_MATROX_MGA_G200:
		printf(MGA_MSG" Found MGA G200 PCI\n");
		is_g400 = 0;
		goto card_found;
#endif
	    }
	}
    }

    if (is_g400 == -1)
    {
	if(verbose)
	  printf(MGA_MSG" Can't find chip\n\n");
	return(ENXIO);
    }

card_found:
    probed = 1;
    memcpy(&pci_info, &lst[i], sizeof(pciinfo_t));

    mga_cap.device_id = pci_info.device; /* set device id in capabilites */

    return(0);
}

int VIDIX_NAME(vixInit)(const char *args)
{
    unsigned int card_option = 0;
    int err;

    /* reset Brightness & Constrast here */
    regs.beslumactl = (0x0 << 16) + 0x80;

    if (mga_verbose) printf(MGA_MSG" init\n");

    mga_vid_in_use = 0;

    if (!probed)
    {
	printf(MGA_MSG" driver was not probed but is being initializing\n");
	return(EINTR);
    }

#ifdef MGA_PCICONFIG_MEMDETECT
    pci_config_read(pci_info.bus, pci_info.card, pci_info.func,
		    0x40, 4, &card_option);
    if (mga_verbose > 1) printf(MGA_MSG" OPTION word: 0x%08X  mem: 0x%02X  %s\n", card_option,
				(card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM");
#endif

    if (mga_ram_size)
    {
	printf(MGA_MSG" RAMSIZE forced to %d MB\n", mga_ram_size);
    }
    else
    {
#ifdef MGA_MEMORY_SIZE
	mga_ram_size = MGA_MEMORY_SIZE;
	printf(MGA_MSG" hard-coded RAMSIZE is %d MB\n", (unsigned int) mga_ram_size);
#else
	if (is_g400)
	{
	    switch((card_option>>10)&0x17)
	    {
	    // SDRAM:
	    case 0x00:
	    case 0x04:  mga_ram_size = 16; break;
	    case 0x03:  mga_ram_size = 32; break;
	    // SGRAM:
	    case 0x10:
	    case 0x14:  mga_ram_size = 32; break;
	    case 0x11:
	    case 0x12:  mga_ram_size = 16; break;
	    default:
		mga_ram_size = 16;
		printf(MGA_MSG" Couldn't detect RAMSIZE, assuming 16MB!\n");
	    }
	}
	else
	{
	    switch((card_option>>10)&0x17)
	    {
		// case 0x10:
		// case 0x13:  mga_ram_size = 8; break;
	    default: mga_ram_size = 8;
	    }
	}

#if 0
	//	    printf("List resources -----------\n");
	for(temp=0;temp<DEVICE_COUNT_RESOURCE;temp++){
	    struct resource *res=&pci_dev->resource[temp];
	    if(res->flags){
		int size=(1+res->end-res->start)>>20;
		printf("res %d:  start: 0x%X   end: 0x%X  (%d MB) flags=0x%X\n",temp,res->start,res->end,size,res->flags);
		if(res->flags&(IORESOURCE_MEM|IORESOURCE_PREFETCH)){
		    if(size>mga_ram_size && size<=64) mga_ram_size=size;
		}
	    }
	}
#endif

	printf(MGA_MSG" detected RAMSIZE is %d MB\n", (unsigned int) mga_ram_size);
#endif
    }

    if (mga_ram_size)
    {
	if ((mga_ram_size < 4) || (mga_ram_size > 64))
	{
	    printf(MGA_MSG" invalid RAMSIZE: %d MB\n", mga_ram_size);
	    return(EINVAL);
	}
    }

    if (mga_verbose > 1) printf(MGA_MSG" hardware addresses: mmio: 0x%lx, framebuffer: 0x%lx\n",
				pci_info.base1, pci_info.base0);

    mga_mmio_base = map_phys_mem(pci_info.base1,0x4000);
    mga_mem_base = map_phys_mem(pci_info.base0,mga_ram_size*1024*1024);

    if (mga_verbose > 1) printf(MGA_MSG" MMIO at %p, IRQ: %d, framebuffer: %p\n",
				mga_mmio_base, mga_irq, mga_mem_base);
    err = mtrr_set_type(pci_info.base0,mga_ram_size*1024*1024,MTRR_TYPE_WRCOMB);
    if(!err) printf(MGA_MSG" Set write-combining type of video memory\n");
#ifdef MGA_ALLOW_IRQ
    if (mga_irq != -1)
    {
	int tmp = request_irq(mga_irq, mga_handle_irq, SA_INTERRUPT | SA_SHIRQ, "Syncfb Time Base", &mga_irq);
	if (tmp)
	{
	    printf("syncfb (mga): cannot register irq %d (Err: %d)\n", mga_irq, tmp);
	    mga_irq=-1;
	}
	else
	{
	    printf("syncfb (mga): registered irq %d\n", mga_irq);
	}
    }
    else
    {
	printf("syncfb (mga): No valid irq was found\n");
	mga_irq=-1;
    }
#else
    printf(MGA_MSG" IRQ support disabled\n");
    mga_irq=-1;
#endif
#ifdef CRTC2
    memset(&cregs_save, 0, sizeof(cregs_save));
#endif
    return(0);
}

void VIDIX_NAME(vixDestroy)(void)
{
    if (mga_verbose) printf(MGA_MSG" destroy\n");

    /* FIXME turn off BES */
    vid_src_ready = 0;
    regs.besctl &= ~1;
    regs.besglobctl &= ~(1<<6);  // UYVY format selected
    //    mga_config.colkey_on=0; //!!!
    mga_vid_write_regs(1);
    mga_vid_in_use = 0;

#ifdef MGA_ALLOW_IRQ
    if (mga_irq != -1)
	free_irq(mga_irq, &mga_irq);
#endif

    if (mga_mmio_base)
	unmap_phys_mem(mga_mmio_base, 0x4000);
    if (mga_mem_base)
	unmap_phys_mem(mga_mem_base, mga_ram_size);
    return;
}

int VIDIX_NAME(vixQueryFourcc)(vidix_fourcc_t *to)
{
    int supports=0;
    if (mga_verbose) printf(MGA_MSG" query fourcc (%x)\n", to->fourcc);

    switch(to->fourcc)
    {
    case IMGFMT_YV12:
    case IMGFMT_IYUV:
    case IMGFMT_I420:
	supports = is_g400 ? 1 : 0;
    case IMGFMT_NV12:
	supports = is_g400 ? 0 : 1;
    case IMGFMT_YUY2:
    case IMGFMT_UYVY:
	supports = 1;
	break;
    default:
	supports = 0;
    }

    if(!supports)
    {
	to->depth = to->flags = 0;
	return(ENOTSUP);
    }
    to->depth = VID_DEPTH_12BPP |
	VID_DEPTH_15BPP | VID_DEPTH_16BPP |
	VID_DEPTH_24BPP | VID_DEPTH_32BPP;
    to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY;
    return(0);
}

unsigned int VIDIX_NAME(vixGetVersion)(void)
{
    return(VIDIX_VERSION);
}

int VIDIX_NAME(vixGetCapability)(vidix_capability_t *to)
{
    memcpy(to, &mga_cap, sizeof(vidix_capability_t));
    return(0);
}

int VIDIX_NAME(vixGetGrKeys)(vidix_grkey_t *grkey)
{
    memcpy(grkey, &mga_grkey, sizeof(vidix_grkey_t));
    return(0);
}

int VIDIX_NAME(vixSetGrKeys)(const vidix_grkey_t *grkey)
{
    memcpy(&mga_grkey, grkey, sizeof(vidix_grkey_t));
    return(0);
}

int VIDIX_NAME(vixPlaybackSetEq)( const vidix_video_eq_t * eq)
{
    uint32_t luma;
    float factor = 255.0 / 2000;

    /* contrast and brightness control isn't supported on G200 - alex */
    if (!is_g400)
    {
	if (mga_verbose) printf(MGA_MSG" equalizer isn't supported with G200\n");
	return(ENOTSUP);
    }

    luma = regs.beslumactl;

    if (eq->cap & VEQ_CAP_BRIGHTNESS)
    {
	luma &= 0xffff;
	luma |= (((int)(eq->brightness * factor) & 0xff) << 16);
    }
    if (eq->cap & VEQ_CAP_CONTRAST)
    {
	luma &= 0xffff << 16;
	luma |= ((int)((eq->contrast + 1000) * factor) & 0xff);
    }

    regs.beslumactl = luma;
#ifdef BES
    writel(BESLUMACTL, regs.beslumactl);
#endif
    return(0);
}

int VIDIX_NAME(vixPlaybackGetEq)( vidix_video_eq_t * eq)
{
    float factor = 2000.0 / 255;

    /* contrast and brightness control isn't supported on G200 - alex */
    if (!is_g400)
    {
	if (mga_verbose) printf(MGA_MSG" equalizer isn't supported with G200\n");
	return(ENOTSUP);
    }

    // BESLUMACTL is WO only registr!
    // this will not work: regs.beslumactl = readl(BESLUMACTL);
    eq->brightness = ((signed char)((regs.beslumactl >> 16) & 0xff)) * factor;
    eq->contrast = (regs.beslumactl & 0xFF) * factor - 1000;
    eq->cap = VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST;

    return(0);
}