cpu.ch

菲斯卡尔无传感器无刷控制方案。具体说明文档和程序都在压缩包内。

#define C_Inhr1_reg_SCI_SCISR                0         /*0x00000000*/

#define C_PWM_A_reg_PWM_PMCCR_bit_ENHA       1         /*0x00000001*/

/* PWM_PMCCR: ENHA=1,nBX=1,MSK=0,??=0,??=0,VLMODE=1,??=0,SWP45=0,SWP23=0,SWP01=0 */
#define C_PWM_A_reg_PWM_PMCCR                49168     /*0x0000C010*/

/* PWM_PMCFG: ??=0,DBG_EN=0,WAIT_EN=0,EDG=1,??=0,TOPNEG45=0,TOPNEG23=0,TOPNEG01=0,??=0,BOTNEG45=0,BOTNEG23=0,BOTNEG01=0,INDEP45=1,INDEP23=1,INDEP01=1,WP=0 */
#define C_PWM_A_reg_PWM_PMCFG                4110      /*0x0000100E*/

#define C_PWM_A_reg_PWM_PMCTL_bit_LDOK       1         /*0x00000001*/

#define C_PWM_A_reg_PWM_PMCTL_bit_PWMEN      1         /*0x00000001*/

/* PWM_PMCTL: LDFQ=0,HALF=0,IPOL2=0,IPOL1=0,IPOL0=0,PRSC=0,PWMRIE=1,PWMF=0,??=0,??=0,LDOK=0,PWMEN=0 */
#define C_PWM_A_reg_PWM_PMCTL                32        /*0x00000020*/

/* PWM_PMDEADTM0: ??=0,??=0,??=0,??=0,PWMDT0=0x20 */
#define C_PWM_A_reg_PWM_PMDEADTM0            32        /*0x00000020*/

/* PWM_PMDEADTM1: ??=0,??=0,??=0,??=0,PWMDT1=0x20 */
#define C_PWM_A_reg_PWM_PMDEADTM1            32        /*0x00000020*/

/* PWM_PMDISMAP1: DISMAP=0 */
#define C_PWM_A_reg_PWM_PMDISMAP1            0         /*0x00000000*/

/* PWM_PMDISMAP2: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DISMAP=0 */
#define C_PWM_A_reg_PWM_PMDISMAP2            0         /*0x00000000*/

/* PWM_PMFCTL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FIE3=0,FMODE3=0,FIE2=0,FMODE2=0,FIE1=0,FMODE1=0,FIE0=1,FMODE0=0 */
#define C_PWM_A_reg_PWM_PMFCTL               2         /*0x00000002*/

/* PWM_PMOUT: PAD_EN=0,??=0,OUTCTL=0,??=0,??=0,OUT=0 */
#define C_PWM_A_reg_PWM_PMOUT                0         /*0x00000000*/

/* PWM_PMSRC: ??=0,??=0,CINV5=0,CINV4=0,CINV3=0,CINV2=0,CINV1=0,CINV0=0,SRC2=0,SRC1=0,SRC0=0 */
#define C_PWM_A_reg_PWM_PMSRC                0         /*0x00000000*/

/* PWM_PWMCM: ??=0,CM=0x0640 */
#define C_PWM_A_reg_PWM_PWMCM                1600      /*0x00000640*/

/* PWM_PWMVAL0: VAL=0 */
#define C_PWM_A_reg_PWM_PWMVAL0              0         /*0x00000000*/

/* PWM_PWMVAL1: VAL=0 */
#define C_PWM_A_reg_PWM_PWMVAL1              0         /*0x00000000*/

/* PWM_PWMVAL2: VAL=0 */
#define C_PWM_A_reg_PWM_PWMVAL2              0         /*0x00000000*/

/* PWM_PWMVAL3: VAL=0 */
#define C_PWM_A_reg_PWM_PWMVAL3              0         /*0x00000000*/

/* PWM_PWMVAL4: VAL=0 */
#define C_PWM_A_reg_PWM_PWMVAL4              0         /*0x00000000*/

/* PWM_PWMVAL5: VAL=0 */
#define C_PWM_A_reg_PWM_PWMVAL5              0         /*0x00000000*/

/* TMR0_CMP1: COMPARISON_1=0 */
#define C_QTIMER_0_reg_TMR0_CMP1             0         /*0x00000000*/

/* TMR0_CMP2: COMPARISON_2=0 */
#define C_QTIMER_0_reg_TMR0_CMP2             0         /*0x00000000*/

/* TMR0_CMPLD1: COMPARATOR_LOAD_1=0 */
#define C_QTIMER_0_reg_TMR0_CMPLD1           0         /*0x00000000*/

/* TMR0_CMPLD2: COMPARATOR_LOAD_2=0 */
#define C_QTIMER_0_reg_TMR0_CMPLD2           0         /*0x00000000*/

/* TMR0_CNTR: COUNTER=0 */
#define C_QTIMER_0_reg_TMR0_CNTR             0         /*0x00000000*/

/* TMR0_COMSCR: DBG_EN=0,??=0,??=0,??=0,??=0,??=0,??=0,TCF2EN=0,TCF1EN=0,TCF2=0,TCF1=0,CL2=0,CL1=0 */
#define C_QTIMER_0_reg_TMR0_COMSCR           0         /*0x00000000*/

/* TMR0_CTRL: CM=1,PCS=0x0D,SCS=0,ONCE=0,LENGTH=0,DIR=0,Co_INIT=0,OM=0 */
#define C_QTIMER_0_reg_TMR0_CTRL             14848     /*0x00003A00*/

/* TMR0_LOAD: LOAD=0 */
#define C_QTIMER_0_reg_TMR0_LOAD             0         /*0x00000000*/

/* TMR0_SCR: TCF=0,TCFIE=0,TOF=0,TOFIE=0,IEF=0,IEFIE=0,IPS=0,INPUT=0,Capture_Mode=0,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=0 */
#define C_QTIMER_0_reg_TMR0_SCR              0         /*0x00000000*/

/* TMR1_CMP1: COMPARISON_1=0x0640 */
#define C_QTIMER_1_reg_TMR1_CMP1             1600      /*0x00000640*/

/* TMR1_CMP2: COMPARISON_2=0 */
#define C_QTIMER_1_reg_TMR1_CMP2             0         /*0x00000000*/

/* TMR1_CMPLD1: COMPARATOR_LOAD_1=0 */
#define C_QTIMER_1_reg_TMR1_CMPLD1           0         /*0x00000000*/

/* TMR1_CMPLD2: COMPARATOR_LOAD_2=0 */
#define C_QTIMER_1_reg_TMR1_CMPLD2           0         /*0x00000000*/

/* TMR1_CNTR: COUNTER=0 */
#define C_QTIMER_1_reg_TMR1_CNTR             0         /*0x00000000*/

/* TMR1_COMSCR: DBG_EN=0,??=0,??=0,??=0,??=0,??=0,??=0,TCF2EN=0,TCF1EN=0,TCF2=0,TCF1=0,CL2=0,CL1=0 */
#define C_QTIMER_1_reg_TMR1_COMSCR           0         /*0x00000000*/

/* TMR1_CTRL: CM=1,PCS=8,SCS=0,ONCE=0,LENGTH=1,DIR=0,Co_INIT=0,OM=0 */
#define C_QTIMER_1_reg_TMR1_CTRL             12320     /*0x00003020*/

/* TMR1_LOAD: LOAD=0 */
#define C_QTIMER_1_reg_TMR1_LOAD             0         /*0x00000000*/

/* TMR1_SCR: TCF=0,TCFIE=1,TOF=0,TOFIE=0,IEF=0,IEFIE=0,IPS=0,INPUT=0,Capture_Mode=0,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=0 */
#define C_QTIMER_1_reg_TMR1_SCR              16384     /*0x00004000*/

/* TMR2_CMP1: COMPARISON_1=0x1900 */
#define C_QTIMER_2_reg_TMR2_CMP1             6400      /*0x00001900*/

/* TMR2_CMP2: COMPARISON_2=0 */
#define C_QTIMER_2_reg_TMR2_CMP2             0         /*0x00000000*/

/* TMR2_CMPLD1: COMPARATOR_LOAD_1=0 */
#define C_QTIMER_2_reg_TMR2_CMPLD1           0         /*0x00000000*/

/* TMR2_CMPLD2: COMPARATOR_LOAD_2=0 */
#define C_QTIMER_2_reg_TMR2_CMPLD2           0         /*0x00000000*/

/* TMR2_CNTR: COUNTER=0 */
#define C_QTIMER_2_reg_TMR2_CNTR             0         /*0x00000000*/

/* TMR2_COMSCR: DBG_EN=0,??=0,??=0,??=0,??=0,??=0,??=0,TCF2EN=0,TCF1EN=0,TCF2=0,TCF1=0,CL2=0,CL1=0 */
#define C_QTIMER_2_reg_TMR2_COMSCR           0         /*0x00000000*/

/* TMR2_CTRL: CM=1,PCS=8,SCS=2,ONCE=0,LENGTH=1,DIR=0,Co_INIT=0,OM=0 */
#define C_QTIMER_2_reg_TMR2_CTRL             12576     /*0x00003120*/

/* TMR2_LOAD: LOAD=0 */
#define C_QTIMER_2_reg_TMR2_LOAD             0         /*0x00000000*/

/* TMR2_SCR: TCF=0,TCFIE=1,TOF=0,TOFIE=0,IEF=0,IEFIE=0,IPS=0,INPUT=0,Capture_Mode=0,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=0 */
#define C_QTIMER_2_reg_TMR2_SCR              16384     /*0x00004000*/

/* TMR3_CMP1: COMPARISON_1=0 */
#define C_QTIMER_3_reg_TMR3_CMP1             0         /*0x00000000*/

/* TMR3_CMP2: COMPARISON_2=0 */
#define C_QTIMER_3_reg_TMR3_CMP2             0         /*0x00000000*/

/* TMR3_CMPLD1: COMPARATOR_LOAD_1=0 */
#define C_QTIMER_3_reg_TMR3_CMPLD1           0         /*0x00000000*/

/* TMR3_CMPLD2: COMPARATOR_LOAD_2=0 */
#define C_QTIMER_3_reg_TMR3_CMPLD2           0         /*0x00000000*/

/* TMR3_CNTR: COUNTER=0x0190 */
#define C_QTIMER_3_reg_TMR3_CNTR             400       /*0x00000190*/

/* TMR3_COMSCR: DBG_EN=0,??=0,??=0,??=0,??=0,??=0,??=0,TCF2EN=0,TCF1EN=0,TCF2=0,TCF1=0,CL2=0,CL1=0 */
#define C_QTIMER_3_reg_TMR3_COMSCR           0         /*0x00000000*/

/* TMR3_CTRL: CM=6,PCS=8,SCS=3,ONCE=0,LENGTH=1,DIR=1,Co_INIT=0,OM=5 */
#define C_QTIMER_3_reg_TMR3_CTRL             53685     /*0x0000D1B5*/

/* TMR3_LOAD: LOAD=0x0190 */
#define C_QTIMER_3_reg_TMR3_LOAD             400       /*0x00000190*/

/* TMR3_SCR: TCF=0,TCFIE=0,TOF=0,TOFIE=0,IEF=0,IEFIE=0,IPS=0,INPUT=0,Capture_Mode=0,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=0 */
#define C_QTIMER_3_reg_TMR3_SCR              0         /*0x00000000*/


/* END Cpu */

/*
** ###################################################################
**
**     This file was created by UNIS Processor Expert 2.96 [03.65]
**     for the Freescale 56800 series of microcontrollers.
**
** ###################################################################
*/