cpu.ch

菲斯卡尔无传感器无刷控制方案。具体说明文档和程序都在压缩包内。

/** ###################################################################
**      THIS MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**      Filename  : Cpu.ch
**      Project   : bldc_zc_8013
**      Date/Time : 24.5.2005, 16:36
**      Abstract  :
**          This file manifest constants for the bean drivers.
**
**      (c) Copyright UNIS, spol. s r.o. 1997-2004
**      UNIS, spol. s r.o.
**      Jundrovska 33
**      624 00 Brno
**      Czech Republic
**      http      : www.processorexpert.com
**      mail      : [e-mail]
**  ##################################################################*/

/* MODULE Cpu */

//used constants
/* ADC_ADCR1: ??=0,STOP0=0,START0=0,SYNC0=1,EOSIE0=1,ZCIE=1,LLMTIE=1,HLMTIE=1,CHNCFG=0,??=0,SMODE=5 */
#define C_ADC_A_reg_ADC_ADCR1                7941      /*0x00001F05*/

/* ADC_ADCR2: ??=0,STOP1=0,START1=0,SYNC1=1,EOSIE1=0,??=0,??=0,??=0,??=0,??=0,SIMULT=1,DIV=7 */
#define C_ADC_A_reg_ADC_ADCR2                4135      /*0x00001027*/

/* ADC_ADHLMT0: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADHLMT0              32760     /*0x00007FF8*/

/* ADC_ADHLMT1: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADHLMT1              32760     /*0x00007FF8*/

/* ADC_ADHLMT2: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADHLMT2              32760     /*0x00007FF8*/

/* ADC_ADHLMT3: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADHLMT3              32760     /*0x00007FF8*/

/* ADC_ADHLMT4: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADHLMT4              32760     /*0x00007FF8*/

/* ADC_ADHLMT5: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADHLMT5              32760     /*0x00007FF8*/

/* ADC_ADHLMT6: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADHLMT6              32760     /*0x00007FF8*/

/* ADC_ADHLMT7: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADHLMT7              32760     /*0x00007FF8*/

/* ADC_ADLLMT0: ??=0,LLMT=0,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADLLMT0              0         /*0x00000000*/

/* ADC_ADLLMT1: ??=0,LLMT=0,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADLLMT1              0         /*0x00000000*/

/* ADC_ADLLMT2: ??=0,LLMT=0,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADLLMT2              0         /*0x00000000*/

/* ADC_ADLLMT3: ??=0,LLMT=0,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADLLMT3              0         /*0x00000000*/

/* ADC_ADLLMT4: ??=0,LLMT=0,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADLLMT4              0         /*0x00000000*/

/* ADC_ADLLMT5: ??=0,LLMT=0,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADLLMT5              0         /*0x00000000*/

/* ADC_ADLLMT6: ??=0,LLMT=0,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADLLMT6              0         /*0x00000000*/

/* ADC_ADLLMT7: ??=0,LLMT=0,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADLLMT7              0         /*0x00000000*/

/* ADC_ADLST1: ??=0,SAMPLE3=0,??=0,SAMPLE2=2,??=0,SAMPLE1=1,??=0,SAMPLE0=0 */
#define C_ADC_A_reg_ADC_ADLST1               528       /*0x00000210*/

/* ADC_ADLST2: ??=0,SAMPLE7=0,??=0,SAMPLE6=6,??=0,SAMPLE5=5,??=0,SAMPLE4=4 */
#define C_ADC_A_reg_ADC_ADLST2               1620      /*0x00000654*/

/* ADC_ADOFS0: ??=0,OFFSET=0,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADOFS0               0         /*0x00000000*/

/* ADC_ADOFS1: ??=0,OFFSET=0,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADOFS1               0         /*0x00000000*/

/* ADC_ADOFS2: ??=0,OFFSET=0,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADOFS2               0         /*0x00000000*/

/* ADC_ADOFS3: ??=0,OFFSET=0,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADOFS3               0         /*0x00000000*/

/* ADC_ADOFS4: ??=0,OFFSET=0,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADOFS4               0         /*0x00000000*/

/* ADC_ADOFS5: ??=0,OFFSET=0,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADOFS5               0         /*0x00000000*/

/* ADC_ADOFS6: ??=0,OFFSET=0,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADOFS6               0         /*0x00000000*/

/* ADC_ADOFS7: ??=0,OFFSET=0,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_ADOFS7               0         /*0x00000000*/

/* ADC_ADPOWER: ASB=0,??=0,??=0,PSTS2=0,PSTS1=0,PSTS0=0,PUDELAY=0x0D,APD=0,PD2=0,PD1=0,PD0=0 */
#define C_ADC_A_reg_ADC_ADPOWER              208       /*0x000000D0*/

/* ADC_ADSDIS: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DS7=1,DS6=0,DS5=0,DS4=0,DS3=1,DS2=0,DS1=0,DS0=0 */
#define C_ADC_A_reg_ADC_ADSDIS               136       /*0x00000088*/

/* ADC_ADZCC: ZCE7=0,ZCE6=3,ZCE5=3,ZCE4=3,ZCE3=0,ZCE2=0,ZCE1=0,ZCE0=0 */
#define C_ADC_A_reg_ADC_ADZCC                16128     /*0x00003F00*/

/* ADC_CAL: SEL_VREFH=0,SEL_VREFLO=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
#define C_ADC_A_reg_ADC_CAL                  0         /*0x00000000*/

/* FMCLKD: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DIVLD=0,PRDIV8=0,DIV=0x28 */
#define C_Cpu_reg_FMCLKD                     40        /*0x00000028*/

/* GPIO_A_DRIVE: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DRIVE=0 */
#define C_Cpu_reg_GPIO_A_DRIVE               0         /*0x00000000*/

/* GPIO_A_PER: PE|=0x3F */
#define C_Cpu_reg_GPIO_A_PER_mask_or         63        /*0x0000003F*/

/* GPIO_B_DRIVE: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DRIVE=0 */
#define C_Cpu_reg_GPIO_B_DRIVE               0         /*0x00000000*/

/* GPIO_B_PER: PE|=0xC0 */
#define C_Cpu_reg_GPIO_B_PER_mask_or         192       /*0x000000C0*/

/* GPIO_C_DRIVE: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DRIVE6=0,DRIVE5=0,DRIVE4=0,??=0,DRIVE2=0,DRIVE1=0,DRIVE0=0 */
#define C_Cpu_reg_GPIO_C_DRIVE               0         /*0x00000000*/

/* GPIO_C_PER: PE6=1,PE5=1,PE4=1,PE2=1,PE1=1,PE0=1 */
#define C_Cpu_reg_GPIO_C_PER_mask_or         119       /*0x00000077*/

/* GPIO_D_DRIVE: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DRIVE=0 */
#define C_Cpu_reg_GPIO_D_DRIVE               0         /*0x00000000*/

#define C_Cpu_reg_INTC_IPR2_mask_and         20800     /*0x00005140*/

#define C_Cpu_reg_INTC_IPR2_mask_or          41600     /*0x0000A280*/

#define C_Cpu_reg_INTC_IPR3_mask_and         1600      /*0x00000640*/

#define C_Cpu_reg_INTC_IPR3_mask_or          51584     /*0x0000C980*/

#define C_Cpu_reg_INTC_IPR4_mask_and         84        /*0x00000054*/

#define C_Cpu_reg_INTC_IPR4_mask_or          168       /*0x000000A8*/

#define C_Cpu_reg_PLLCR_bit_PRECS            0         /*0x00000000*/

/* PLLDB: LORTP=2,??=0,PLLCOD=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
#define C_Cpu_reg_PLLDB                      8192      /*0x00002000*/

/* SIM_CONTROL: TC3_SD=0,TC2_SD=0,TC1_SD=0,TC0_SD=0,SCI_SD=0,??=0,TC3_INP=0,??=0,??=0,??=0,OnceEbl=1,SWRst=0,stop_disable=0,wait_disable=0 */
#define C_Cpu_reg_SIM_CONTROL                32        /*0x00000020*/

/* SIM_GPS: CFG_B7=0,CFG_B6=0 */
#define C_Cpu_reg_SIM_GPS_mask_and_0         3072      /*0x00000C00*/

/* SIM_GPS: TCR=0,PCR=0 */
#define C_Cpu_reg_SIM_GPS_mask_and           49152     /*0x0000C000*/

/* SIM_PCE: I2C=0,??=0,ADC=1,??=0,??=0,??=0,??=0,??=0,??=0,TMR=1,??=0,SCI=1,??=0,SPI=0,??=0,PWM=1 */
#define C_Cpu_reg_SIM_PCE                    8273      /*0x00002051*/

/* SCI_SCIBR: ??=0,??=0,??=0,SBR=0xD0 */
#define C_Inhr1_reg_SCI_SCIBR                208       /*0x000000D0*/

#define C_Inhr1_reg_SCI_SCICR_bit_TEIE_0     0         /*0x00000000*/

#define C_Inhr1_reg_SCI_SCICR_bit_TEIE       1         /*0x00000001*/

/* SCI_SCICR: LOOP=0,SWAI=0,RSRC=0,M=0,WAKE=0,POL=0,PE=0,PT=0,TEIE=0,TIIE=0,RFIE=0,REIE=0,TE=0,RE=0,RWU=0,SBK=0 */
#define C_Inhr1_reg_SCI_SCICR                0         /*0x00000000*/

/* SCI_SCISR: TDRE=0,TIDLE=0,RDRF=0,RIDLE=0,OR=0,NF=0,FE=0,PF=0,??=0,??=0,??=0,??=0,LSE=0,??=0,??=0,RAF=0 */