adc_a.c

菲斯卡尔无传感器无刷控制方案。具体说明文档和程序都在压缩包内。

/** ###################################################################
**     THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename  : ADC_A.C
**     Project   : bldc_zc_8013
**     Processor : 56F8013VFAE
**     Beantype  : Init_ADC
**     Version   : Bean 01.196, Driver 01.13, CPU db: 2.87.068
**     Compiler  : Metrowerks DSP C Compiler
**     Date/Time : 23.5.2005, 11:21
**     Abstract  :
**         This "Init_ADC" Peripheral Inspector implements the
**         Analog-to-Digital converter module (ADC), basic 
**         initialization and settings.
**     Settings  :
**         A/D converter device        : ADC
**
**         A/D setting
**             Mode                    : Triggered Parallel
**             Trigger                 : SYNC input or START bit
**
**         Clock setting
**             Divisor                 : 8
**             A/D frequency           : 2 MHz
**
**         Interrupts
**             End of scan 0 interrupt : Enabled
**             ISR name                : IsrADCEndOfScan
**             Interrupt name          : INT_ADCA_Complete
**             Priority                : 2
**
**             End of scan 1 interrupt : Disabled
**
**             Zero crossing interrupt : Enabled
**             High limit interrupt    : Enabled
**             Low limit interrupt     : Enabled
**             ISR name                : IsrADCLimit
**             Interrupt name          : INT_ADC_ZC_LE
**             Priority                : 1
**
**     Contents  :
**         Init - void ADC_A_Init(void);
**
**     (c) Copyright UNIS, spol. s r.o. 1997-2004
**     UNIS, spol. s r.o.
**     Jundrovska 33
**     624 00 Brno
**     Czech Republic
**     http      : www.processorexpert.com
**     mail      : [e-mail]
** ###################################################################*/

/* MODULE ADC_A. */

#include "ADC_A.h"

/*
** ###################################################################
**
**  The following method(s) must be implemented by the user in one
**  of the following modules:
**
**    #pragma interrupt
**    void IsrADCEndOfScan(void)
**
**    #pragma interrupt
**    void IsrADCLimit(void)
**
**  Modules:
**       bldc_zc_8013
**
** ###################################################################
*/

/*
** ===================================================================
**     Method      :  ADC_A_Init (bean Init_ADC)
**
**     Description :
**         This method initializes registers of the ADC module
**         according to this Peripheral Initialization Bean settings.
**         Call this method in the user code to initialize the
**         module. By default, the method is called by PE
**         automatically; see "Call Init method" property of the
**         bean for more details.
**     Parameters  : None
**     Returns     : Nothing
** ===================================================================
*/
void ADC_A_Init(void)
{
  /* ADC_ADSDIS: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DS7=1,DS6=0,DS5=0,DS4=0,DS3=1,DS2=0,DS1=0,DS0=0 */
  setReg16(ADC_ADSDIS,C_ADC_A_reg_ADC_ADSDIS); /* Set sample disable register */ 
  /* ADC_ADLST1: ??=0,SAMPLE3=0,??=0,SAMPLE2=2,??=0,SAMPLE1=1,??=0,SAMPLE0=0 */
  setReg16(ADC_ADLST1,C_ADC_A_reg_ADC_ADLST1); /* Set channel list register 1 */ 
  /* ADC_ADLST2: ??=0,SAMPLE7=0,??=0,SAMPLE6=6,??=0,SAMPLE5=5,??=0,SAMPLE4=4 */
  setReg16(ADC_ADLST2,C_ADC_A_reg_ADC_ADLST2); /* Set channel list register 2 */ 
  /* ADC_ADLLMT0: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC_ADLLMT0,C_ADC_A_reg_ADC_ADLLMT0); /* Set low limit register 0 */ 
  /* ADC_ADLLMT1: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC_ADLLMT1,C_ADC_A_reg_ADC_ADLLMT1); /* Set low limit register 1 */ 
  /* ADC_ADLLMT2: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC_ADLLMT2,C_ADC_A_reg_ADC_ADLLMT2); /* Set low limit register 2 */ 
  /* ADC_ADLLMT3: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC_ADLLMT3,C_ADC_A_reg_ADC_ADLLMT3); /* Set low limit register 3 */ 
  /* ADC_ADLLMT4: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC_ADLLMT4,C_ADC_A_reg_ADC_ADLLMT4); /* Set low limit register 4 */ 
  /* ADC_ADLLMT5: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC_ADLLMT5,C_ADC_A_reg_ADC_ADLLMT5); /* Set low limit register 5 */ 
  /* ADC_ADLLMT6: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC_ADLLMT6,C_ADC_A_reg_ADC_ADLLMT6); /* Set low limit register 6 */ 
  /* ADC_ADLLMT7: ??=0,LLMT=0,??=0,??=0,??=0 */
  setReg16(ADC_ADLLMT7,C_ADC_A_reg_ADC_ADLLMT7); /* Set low limit register 7 */ 
  /* ADC_ADHLMT0: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC_ADHLMT0,C_ADC_A_reg_ADC_ADHLMT0); /* Set high limit register 0 */ 
  /* ADC_ADHLMT1: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC_ADHLMT1,C_ADC_A_reg_ADC_ADHLMT1); /* Set high limit register 1 */ 
  /* ADC_ADHLMT2: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC_ADHLMT2,C_ADC_A_reg_ADC_ADHLMT2); /* Set high limit register 2 */ 
  /* ADC_ADHLMT3: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC_ADHLMT3,C_ADC_A_reg_ADC_ADHLMT3); /* Set high limit register 3 */ 
  /* ADC_ADHLMT4: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC_ADHLMT4,C_ADC_A_reg_ADC_ADHLMT4); /* Set high limit register 4 */ 
  /* ADC_ADHLMT5: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC_ADHLMT5,C_ADC_A_reg_ADC_ADHLMT5); /* Set high limit register 5 */ 
  /* ADC_ADHLMT6: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC_ADHLMT6,C_ADC_A_reg_ADC_ADHLMT6); /* Set high limit register 6 */ 
  /* ADC_ADHLMT7: ??=0,HLMT=0x0FFF,??=0,??=0,??=0 */
  setReg16(ADC_ADHLMT7,C_ADC_A_reg_ADC_ADHLMT7); /* Set high limit register 7 */ 
  /* ADC_ADOFS0: ??=0,OFFSET=0,??=0,??=0,??=0 */
  setReg16(ADC_ADOFS0,C_ADC_A_reg_ADC_ADOFS0); /* Set offset register 0 */ 
  /* ADC_ADOFS1: ??=0,OFFSET=0,??=0,??=0,??=0 */
  setReg16(ADC_ADOFS1,C_ADC_A_reg_ADC_ADOFS1); /* Set offset register 1 */ 
  /* ADC_ADOFS2: ??=0,OFFSET=0,??=0,??=0,??=0 */
  setReg16(ADC_ADOFS2,C_ADC_A_reg_ADC_ADOFS2); /* Set offset register 2 */ 
  /* ADC_ADOFS3: ??=0,OFFSET=0,??=0,??=0,??=0 */
  setReg16(ADC_ADOFS3,C_ADC_A_reg_ADC_ADOFS3); /* Set offset register 3 */ 
  /* ADC_ADOFS4: ??=0,OFFSET=0,??=0,??=0,??=0 */
  setReg16(ADC_ADOFS4,C_ADC_A_reg_ADC_ADOFS4); /* Set offset register 4 */ 
  /* ADC_ADOFS5: ??=0,OFFSET=0,??=0,??=0,??=0 */
  setReg16(ADC_ADOFS5,C_ADC_A_reg_ADC_ADOFS5); /* Set offset register 5 */ 
  /* ADC_ADOFS6: ??=0,OFFSET=0,??=0,??=0,??=0 */
  setReg16(ADC_ADOFS6,C_ADC_A_reg_ADC_ADOFS6); /* Set offset register 6 */ 
  /* ADC_ADOFS7: ??=0,OFFSET=0,??=0,??=0,??=0 */
  setReg16(ADC_ADOFS7,C_ADC_A_reg_ADC_ADOFS7); /* Set offset register 7 */ 
  /* ADC_ADZCC: ZCE7=0,ZCE6=3,ZCE5=3,ZCE4=3,ZCE3=0,ZCE2=0,ZCE1=0,ZCE0=0 */
  setReg16(ADC_ADZCC,C_ADC_A_reg_ADC_ADZCC); /* Set zero crossing control register */ 
  /* ADC_CAL: SEL_VREFH=0,SEL_VREFLO=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  setReg16(ADC_CAL,C_ADC_A_reg_ADC_CAL); /* Set AD calibration mode and references */ 
  /* ADC_ADCR2: ??=0,STOP1=0,START1=0,SYNC1=1,EOSIE1=0,??=0,??=0,??=0,??=0,??=0,SIMULT=1,DIV=7 */
  setReg16(ADC_ADCR2,C_ADC_A_reg_ADC_ADCR2); /* Set control register 2 */ 
  /* ADC_ADCR1: ??=0,STOP0=0,START0=0,SYNC0=1,EOSIE0=1,ZCIE=1,LLMTIE=1,HLMTIE=1,CHNCFG=0,??=0,SMODE=5 */
  setReg16(ADC_ADCR1,C_ADC_A_reg_ADC_ADCR1); /* Set control register 1 */ 
  /* ADC_ADPOWER: ASB=0,??=0,??=0,PSTS2=0,PSTS1=0,PSTS0=0,PUDELAY=0x0D,APD=0,PD2=0,PD1=0,PD0=0 */
  setReg16(ADC_ADPOWER,C_ADC_A_reg_ADC_ADPOWER); /* Set power control register */ 
}

/* END ADC_A. */

/*
** ###################################################################
**
**     This file was created by UNIS Processor Expert 2.96 [03.65]
**     for the Freescale 56800 series of microcontrollers.
**
** ###################################################################
*/