io_map.h

菲斯卡尔无传感器无刷控制方案。具体说明文档和程序都在压缩包内。

  /*** TMR1_CNTR - Timer Channel 1 Counter Register; 0x0000F015 ***/
  union {
    word Word;
  } TMR1_CNTR_STR;
  
  #define TMR1_CNTR                     *((volatile word *)0x0000F015)


  /*** TMR1_CTRL - Timer Channel 1 Control Register; 0x0000F016 ***/
  union {
    word Word;
  } TMR1_CTRL_STR;
  
  #define TMR1_CTRL_OM0_MASK            0x01U
  #define TMR1_CTRL_OM1_MASK            0x02U
  #define TMR1_CTRL_OM2_MASK            0x04U
  #define TMR1_CTRL_Co_INIT_MASK        0x08U
  #define TMR1_CTRL_DIR_MASK            0x10U
  #define TMR1_CTRL_LENGTH_MASK         0x20U
  #define TMR1_CTRL_ONCE_MASK           0x40U
  #define TMR1_CTRL_SCS0_MASK           0x80U
  #define TMR1_CTRL_SCS1_MASK           0x0100U
  #define TMR1_CTRL_PCS0_MASK           0x0200U
  #define TMR1_CTRL_PCS1_MASK           0x0400U
  #define TMR1_CTRL_PCS2_MASK           0x0800U
  #define TMR1_CTRL_PCS3_MASK           0x1000U
  #define TMR1_CTRL_CM0_MASK            0x2000U
  #define TMR1_CTRL_CM1_MASK            0x4000U
  #define TMR1_CTRL_CM2_MASK            0x8000U
  #define TMR1_CTRL_OM_MASK             0x07U
  #define TMR1_CTRL_OM_BITNUM           0x00U
  #define TMR1_CTRL_SCS_MASK            0x0180U
  #define TMR1_CTRL_SCS_BITNUM          0x07U
  #define TMR1_CTRL_PCS_MASK            0x1E00U
  #define TMR1_CTRL_PCS_BITNUM          0x09U
  #define TMR1_CTRL_CM_MASK             0xE000U
  #define TMR1_CTRL_CM_BITNUM           0x0DU
  #define TMR1_CTRL                     *((volatile word *)0x0000F016)


  /*** TMR1_SCR - Timer Channel 1 Status and Control Register; 0x0000F017 ***/
  union {
    word Word;
  } TMR1_SCR_STR;
  
  #define TMR1_SCR_OEN_MASK             0x01U
  #define TMR1_SCR_OPS_MASK             0x02U
  #define TMR1_SCR_FORCE_MASK           0x04U
  #define TMR1_SCR_VAL_MASK             0x08U
  #define TMR1_SCR_EEOF_MASK            0x10U
  #define TMR1_SCR_MSTR_MASK            0x20U
  #define TMR1_SCR_Capture_Mode0_MASK   0x40U
  #define TMR1_SCR_Capture_Mode1_MASK   0x80U
  #define TMR1_SCR_INPUT_MASK           0x0100U
  #define TMR1_SCR_IPS_MASK             0x0200U
  #define TMR1_SCR_IEFIE_MASK           0x0400U
  #define TMR1_SCR_IEF_MASK             0x0800U
  #define TMR1_SCR_TOFIE_MASK           0x1000U
  #define TMR1_SCR_TOF_MASK             0x2000U
  #define TMR1_SCR_TCFIE_MASK           0x4000U
  #define TMR1_SCR_TCF_MASK             0x8000U
  #define TMR1_SCR_Capture_Mode_MASK    0xC0U
  #define TMR1_SCR_Capture_Mode_BITNUM  0x06U
  #define TMR1_SCR                      *((volatile word *)0x0000F017)


  /*** TMR1_CMPLD1 - Timer Channel 1 Comparator Load Register 1; 0x0000F018 ***/
  union {
    word Word;
  } TMR1_CMPLD1_STR;
  
  #define TMR1_CMPLD1_COMPARATOR_LOAD_10_MASK 0x01U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_11_MASK 0x02U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_12_MASK 0x04U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_13_MASK 0x08U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_14_MASK 0x10U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_15_MASK 0x20U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_16_MASK 0x40U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_17_MASK 0x80U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_18_MASK 0x0100U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_19_MASK 0x0200U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_110_MASK 0x0400U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_111_MASK 0x0800U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_112_MASK 0x1000U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_113_MASK 0x2000U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_114_MASK 0x4000U
  #define TMR1_CMPLD1_COMPARATOR_LOAD_115_MASK 0x8000U
  #define TMR1_CMPLD1                   *((volatile word *)0x0000F018)


  /*** TMR1_CMPLD2 - Timer Channel 1 Comparator Load Register 2; 0x0000F019 ***/
  union {
    word Word;
  } TMR1_CMPLD2_STR;
  
  #define TMR1_CMPLD2_COMPARATOR_LOAD_20_MASK 0x01U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_21_MASK 0x02U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_22_MASK 0x04U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_23_MASK 0x08U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_24_MASK 0x10U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_25_MASK 0x20U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_26_MASK 0x40U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_27_MASK 0x80U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_28_MASK 0x0100U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_29_MASK 0x0200U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_210_MASK 0x0400U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_211_MASK 0x0800U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_212_MASK 0x1000U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_213_MASK 0x2000U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_214_MASK 0x4000U
  #define TMR1_CMPLD2_COMPARATOR_LOAD_215_MASK 0x8000U
  #define TMR1_CMPLD2                   *((volatile word *)0x0000F019)


  /*** TMR1_COMSCR - Timer Channel 1 Comparator Status and Control Register; 0x0000F01A ***/
  union {
    word Word;
  } TMR1_COMSCR_STR;
  
  #define TMR1_COMSCR_CL10_MASK         0x01U
  #define TMR1_COMSCR_CL11_MASK         0x02U
  #define TMR1_COMSCR_CL20_MASK         0x04U
  #define TMR1_COMSCR_CL21_MASK         0x08U
  #define TMR1_COMSCR_TCF1_MASK         0x10U
  #define TMR1_COMSCR_TCF2_MASK         0x20U
  #define TMR1_COMSCR_TCF1EN_MASK       0x40U
  #define TMR1_COMSCR_TCF2EN_MASK       0x80U
  #define TMR1_COMSCR_DBG_EN0_MASK      0x4000U
  #define TMR1_COMSCR_DBG_EN1_MASK      0x8000U
  #define TMR1_COMSCR_CL1_MASK          0x03U
  #define TMR1_COMSCR_CL1_BITNUM        0x00U
  #define TMR1_COMSCR_CL2_MASK          0x0CU
  #define TMR1_COMSCR_CL2_BITNUM        0x02U
  #define TMR1_COMSCR_TCF_1_MASK        0x30U
  #define TMR1_COMSCR_TCF_1_BITNUM      0x04U
  #define TMR1_COMSCR_DBG_EN_MASK       0xC000U
  #define TMR1_COMSCR_DBG_EN_BITNUM     0x0EU
  #define TMR1_COMSCR                   *((volatile word *)0x0000F01A)


  word Reserved0[5];                   /* Reserved (unused) registers */

} TMR1_PRPH;

/******************************************
*** Peripheral TMR2
*******************************************/
typedef volatile struct {
  /*** TMR2_CMP1 - Timer Channel 2 Compare Register #1; 0x0000F020 ***/
  union {
    word Word;
  } TMR2_CMP1_STR;
  
  #define TMR2_CMP1                     *((volatile word *)0x0000F020)


  /*** TMR2_CMP2 - Timer Channel 2 Compare Register #2; 0x0000F021 ***/
  union {
    word Word;
  } TMR2_CMP2_STR;
  
  #define TMR2_CMP2                     *((volatile word *)0x0000F021)


  /*** TMR2_CAP - Timer Channel 2 Capture Register; 0x0000F022 ***/
  union {
    word Word;
  } TMR2_CAP_STR;
  
  #define TMR2_CAP                      *((volatile word *)0x0000F022)


  /*** TMR2_LOAD - Timer Channel 2 Load Register; 0x0000F023 ***/
  union {
    word Word;
  } TMR2_LOAD_STR;
  
  #define TMR2_LOAD_LOAD0_MASK          0x01U
  #define TMR2_LOAD_LOAD1_MASK          0x02U
  #define TMR2_LOAD_LOAD2_MASK          0x04U
  #define TMR2_LOAD_LOAD3_MASK          0x08U
  #define TMR2_LOAD_LOAD4_MASK          0x10U
  #define TMR2_LOAD_LOAD5_MASK          0x20U
  #define TMR2_LOAD_LOAD6_MASK          0x40U
  #define TMR2_LOAD_LOAD7_MASK          0x80U
  #define TMR2_LOAD_LOAD8_MASK          0x0100U
  #define TMR2_LOAD_LOAD9_MASK          0x0200U
  #define TMR2_LOAD_LOAD10_MASK         0x0400U
  #define TMR2_LOAD_LOAD11_MASK         0x0800U
  #define TMR2_LOAD_LOAD12_MASK         0x1000U
  #define TMR2_LOAD_LOAD13_MASK         0x2000U
  #define TMR2_LOAD_LOAD14_MASK         0x4000U
  #define TMR2_LOAD_LOAD15_MASK         0x8000U
  #define TMR2_LOAD                     *((volatile word *)0x0000F023)


  /*** TMR2_HOLD - Timer Channel 2 Hold Register; 0x0000F024 ***/
  union {
    word Word;
  } TMR2_HOLD_STR;
  
  #define TMR2_HOLD_HOLD0_MASK          0x01U
  #define TMR2_HOLD_HOLD1_MASK          0x02U
  #define TMR2_HOLD_HOLD2_MASK          0x04U
  #define TMR2_HOLD_HOLD3_MASK          0x08U
  #define TMR2_HOLD_HOLD4_MASK          0x10U
  #define TMR2_HOLD_HOLD5_MASK          0x20U
  #define TMR2_HOLD_HOLD6_MASK          0x40U
  #define TMR2_HOLD_HOLD7_MASK          0x80U
  #define TMR2_HOLD_HOLD8_MASK          0x0100U
  #define TMR2_HOLD_HOLD9_MASK          0x0200U
  #define TMR2_HOLD_HOLD10_MASK         0x0400U
  #define TMR2_HOLD_HOLD11_MASK         0x0800U
  #define TMR2_HOLD_HOLD12_MASK         0x1000U
  #define TMR2_HOLD_HOLD13_MASK         0x2000U
  #define TMR2_HOLD_HOLD14_MASK         0x4000U
  #define TMR2_HOLD_HOLD15_MASK         0x8000U
  #define TMR2_HOLD                     *((volatile word *)0x0000F024)


  /*** TMR2_CNTR - Timer Channel 2 Counter Register; 0x0000F025 ***/
  union {
    word Word;
  } TMR2_CNTR_STR;
  
  #define TMR2_CNTR                     *((volatile word *)0x0000F025)


  /*** TMR2_CTRL - Timer Channel 2 Control Register; 0x0000F026 ***/
  union {
    word Word;
  } TMR2_CTRL_STR;
  
  #define TMR2_CTRL_OM0_MASK            0x01U
  #define TMR2_CTRL_OM1_MASK            0x02U
  #define TMR2_CTRL_OM2_MASK            0x04U
  #define TMR2_CTRL_Co_INIT_MASK        0x08U
  #define TMR2_CTRL_DIR_MASK            0x10U
  #define TMR2_CTRL_LENGTH_MASK         0x20U
  #define TMR2_CTRL_ONCE_MASK           0x40U
  #define TMR2_CTRL_SCS0_MASK           0x80U
  #define TMR2_CTRL_SCS1_MASK           0x0100U
  #define TMR2_CTRL_PCS0_MASK           0x0200U
  #define TMR2_CTRL_PCS1_MASK           0x0400U
  #define TMR2_CTRL_PCS2_MASK           0x0800U
  #define TMR2_CTRL_PCS3_MASK           0x1000U
  #define TMR2_CTRL_CM0_MASK            0x2000U
  #define TMR2_CTRL_CM1_MASK            0x4000U
  #define TMR2_CTRL_CM2_MASK            0x8000U
  #define TMR2_CTRL_OM_MASK             0x07U
  #define TMR2_CTRL_OM_BITNUM           0x00U
  #define TMR2_CTRL_SCS_MASK            0x0180U
  #define TMR2_CTRL_SCS_BITNUM          0x07U
  #define TMR2_CTRL_PCS_MASK            0x1E00U
  #define TMR2_CTRL_PCS_BITNUM          0x09U
  #define TMR2_CTRL_CM_MASK             0xE000U
  #define TMR2_CTRL_CM_BITNUM           0x0DU
  #define TMR2_CTRL                     *((volatile word *)0x0000F026)


  /*** TMR2_SCR - Timer Channel 2 Status and Control Register; 0x0000F027 ***/
  union {
    word Word;
  } TMR2_SCR_STR;
  
  #define TMR2_SCR_OEN_MASK             0x01U
  #define TMR2_SCR_OPS_MASK             0x02U
  #define TMR2_SCR_FORCE_MASK           0x04U
  #define TMR2_SCR_VAL_MASK             0x08U
  #define TMR2_SCR_EEOF_MASK            0x10U
  #define TMR2_SCR_MSTR_MASK            0x20U
  #define TMR2_SCR_Capture_Mode0_MASK   0x40U
  #define TMR2_SCR_Capture_Mode1_MASK   0x80U
  #define TMR2_SCR_INPUT_MASK           0x0100U
  #define TMR2_SCR_IPS_MASK             0x0200U
  #define TMR2_SCR_IEFIE_MASK           0x0400U
  #define TMR2_SCR_IEF_MASK             0x0800U
  #define TMR2_SCR_TOFIE_MASK           0x1000U
  #define TMR2_SCR_TOF_MASK             0x2000U
  #define TMR2_SCR_TCFIE_MASK           0x4000U
  #define TMR2_SCR_TCF_MASK             0x8000U
  #define TMR2_SCR_Capture_Mode_MASK    0xC0U
  #define TMR2_SCR_Capture_Mode_BITNUM  0x06U
  #define TMR2_SCR                      *((volatile word *)0x0000F027)


  /*** TMR2_CMPLD1 - Timer Channel 2 Comparator Load Register 1; 0x0000F028 ***/
  union {
    word Word;
  } TMR2_CMPLD1_STR;
  
  #define TMR2_CMPLD1_COMPARATOR_LOAD_10_MASK 0x01U
  #define TMR2_CMPLD1_COMPARATOR_LOAD_11_MASK 0x02U
  #define TMR2_CMPLD1_COMPARATOR_LOAD_12_MASK 0x04U
  #define TMR2_CMPLD1_COMPARATOR_LOAD_13_MASK 0x08U
  #define TMR2_CMPLD1_COMPARATOR_LOAD_14_MASK 0x10U
  #define TMR2_CMPLD1_COMPARATOR_LOAD_15_MASK 0x20U
  #define TMR2_CMPLD1_COMPARATOR_LOAD_16_MASK 0x40U
  #define TMR2_CMPLD1_COMPARATOR_LOAD_17_MASK 0x80U
  #define TMR2_CMPLD1_COMPARATOR_LOAD_18_MASK 0x0100U
  #define TMR2_CMPLD1_COMPARATOR_LOAD_19_MASK 0x0200U
  #define TMR2_CMPLD1_COMPARATOR_LOAD_110_MASK 0x0400U
  #define TMR2_CMPLD1_COMPARATOR_LOAD_111_MASK 0x0800U
  #define TMR2_CMPLD1_COMPARATOR_LOAD_112_MASK 0x1000U
  #define TMR2_CMPLD1_COMPARATOR_LOAD_113_MASK 0x2000U
  #define TMR2_CMPLD1_COMPARATOR_LOAD_114_MASK 0x4000U
  #define TMR2_CMPLD1_COMPARATOR_LOAD_115_MASK 0x8000U
  #define TMR2_CMPLD1                   *((volatile word *)0x0000F028)


  /*** TMR2_CMPLD2 - Timer Channel 2 Comparator Load Register 2; 0x0000F029 ***/
  union {
    word Word;
  } TMR2_CMPLD2_STR;
  
  #define TMR2_CMPLD2_COMPARATOR_LOAD_20_MASK 0x01U
  #define TMR2_CMPLD2_COMPARATOR_LOAD_21_MASK 0x02U
  #define TMR2_CMPLD2_COMPARATOR_LOAD_22_MASK 0x04U
  #define TMR2_CMPLD2_COMPARATOR_LOAD_23_MASK 0x08U
  #define TMR2_CMPLD2_COMPARATOR_LOAD_24_MASK 0x10U
  #define TMR2_CMPLD2_COMPARATOR_LOAD_25_MASK 0x20U
  #define TMR2_CMPLD2_COMPARATOR_LOAD_26_MASK 0x40U
  #define TMR2_CMPLD2_COMPARATOR_LOAD_27_MASK 0x80U
  #define TMR2_CMPLD2_COMPARATOR_LOAD_28_MASK 0x0100U
  #define TMR2_CMPLD2_COMPARATOR_LOAD_29_MASK 0x0200U
  #define TMR2_CMPLD2_COMPARATOR_LOAD_210_MASK 0x0400U
  #define TMR2_CMPLD2_COMPARATOR_LOAD_211_MASK 0x0800U
  #define TMR2_CMPLD2_COMPARATOR_LOAD_212_MASK 0x1000U
  #define TMR2_CMPLD2_COMPARATOR_LOAD_213_MASK 0x2000U
  #define TMR2_CMPLD2_COMPARATOR_LOAD_214_MASK 0x4000U
  #define TMR2_CMPLD2_COMPARATOR_LOAD_215_MASK 0x8000U