📄 io_map.h
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/** ###################################################################
** THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
** Filename : IO_Map.H
** Project : bldc_zc_8013
** Processor : 56F8013VFAE
** Beantype : IO_Map
** Version : Driver 01.00
** Compiler : Metrowerks DSP C Compiler
** Date/Time : 23.5.2005, 11:21
** Abstract :
** IO_Map.h - implements an IO device's mapping.
** This module contains symbol definitions of all peripheral
** registers and bits.
** Settings :
**
** Contents :
** No public methods
**
** (c) Copyright UNIS, spol. s r.o. 1997-2004
** UNIS, spol. s r.o.
** Jundrovska 33
** 624 00 Brno
** Czech Republic
** http : www.processorexpert.com
** mail : info@processorexpert.com
** ###################################################################*/
#ifndef __IO_Map_H
#define __IO_Map_H
/* Based on CPU DB 56F8013VFAE, version 2.87.067 (RegistersPrg V1.103) */
/* DataSheet : MC56F8300UM/D - Rev. 1.0 */
#include "PE_Types.h"
/******************************************
*** Peripheral TMR0
*******************************************/
typedef volatile struct {
/*** TMR0_CMP1 - Timer Channel 0 Compare Register #1; 0x0000F000 ***/
union {
word Word;
} TMR0_CMP1_STR;
#define TMR0_CMP1 *((volatile word *)0x0000F000)
/*** TMR0_CMP2 - Timer Channel 0 Compare Register #2; 0x0000F001 ***/
union {
word Word;
} TMR0_CMP2_STR;
#define TMR0_CMP2 *((volatile word *)0x0000F001)
/*** TMR0_CAP - Timer Channel 0 Capture Register; 0x0000F002 ***/
union {
word Word;
} TMR0_CAP_STR;
#define TMR0_CAP *((volatile word *)0x0000F002)
/*** TMR0_LOAD - Timer Channel 0 Load Register; 0x0000F003 ***/
union {
word Word;
} TMR0_LOAD_STR;
#define TMR0_LOAD_LOAD0_MASK 0x01U
#define TMR0_LOAD_LOAD1_MASK 0x02U
#define TMR0_LOAD_LOAD2_MASK 0x04U
#define TMR0_LOAD_LOAD3_MASK 0x08U
#define TMR0_LOAD_LOAD4_MASK 0x10U
#define TMR0_LOAD_LOAD5_MASK 0x20U
#define TMR0_LOAD_LOAD6_MASK 0x40U
#define TMR0_LOAD_LOAD7_MASK 0x80U
#define TMR0_LOAD_LOAD8_MASK 0x0100U
#define TMR0_LOAD_LOAD9_MASK 0x0200U
#define TMR0_LOAD_LOAD10_MASK 0x0400U
#define TMR0_LOAD_LOAD11_MASK 0x0800U
#define TMR0_LOAD_LOAD12_MASK 0x1000U
#define TMR0_LOAD_LOAD13_MASK 0x2000U
#define TMR0_LOAD_LOAD14_MASK 0x4000U
#define TMR0_LOAD_LOAD15_MASK 0x8000U
#define TMR0_LOAD *((volatile word *)0x0000F003)
/*** TMR0_HOLD - Timer Channel 0 Hold Register; 0x0000F004 ***/
union {
word Word;
} TMR0_HOLD_STR;
#define TMR0_HOLD_HOLD0_MASK 0x01U
#define TMR0_HOLD_HOLD1_MASK 0x02U
#define TMR0_HOLD_HOLD2_MASK 0x04U
#define TMR0_HOLD_HOLD3_MASK 0x08U
#define TMR0_HOLD_HOLD4_MASK 0x10U
#define TMR0_HOLD_HOLD5_MASK 0x20U
#define TMR0_HOLD_HOLD6_MASK 0x40U
#define TMR0_HOLD_HOLD7_MASK 0x80U
#define TMR0_HOLD_HOLD8_MASK 0x0100U
#define TMR0_HOLD_HOLD9_MASK 0x0200U
#define TMR0_HOLD_HOLD10_MASK 0x0400U
#define TMR0_HOLD_HOLD11_MASK 0x0800U
#define TMR0_HOLD_HOLD12_MASK 0x1000U
#define TMR0_HOLD_HOLD13_MASK 0x2000U
#define TMR0_HOLD_HOLD14_MASK 0x4000U
#define TMR0_HOLD_HOLD15_MASK 0x8000U
#define TMR0_HOLD *((volatile word *)0x0000F004)
/*** TMR0_CNTR - Timer Channel 0 Counter Register; 0x0000F005 ***/
union {
word Word;
} TMR0_CNTR_STR;
#define TMR0_CNTR *((volatile word *)0x0000F005)
/*** TMR0_CTRL - Timer Channel 0 Control Register; 0x0000F006 ***/
union {
word Word;
} TMR0_CTRL_STR;
#define TMR0_CTRL_OM0_MASK 0x01U
#define TMR0_CTRL_OM1_MASK 0x02U
#define TMR0_CTRL_OM2_MASK 0x04U
#define TMR0_CTRL_Co_INIT_MASK 0x08U
#define TMR0_CTRL_DIR_MASK 0x10U
#define TMR0_CTRL_LENGTH_MASK 0x20U
#define TMR0_CTRL_ONCE_MASK 0x40U
#define TMR0_CTRL_SCS0_MASK 0x80U
#define TMR0_CTRL_SCS1_MASK 0x0100U
#define TMR0_CTRL_PCS0_MASK 0x0200U
#define TMR0_CTRL_PCS1_MASK 0x0400U
#define TMR0_CTRL_PCS2_MASK 0x0800U
#define TMR0_CTRL_PCS3_MASK 0x1000U
#define TMR0_CTRL_CM0_MASK 0x2000U
#define TMR0_CTRL_CM1_MASK 0x4000U
#define TMR0_CTRL_CM2_MASK 0x8000U
#define TMR0_CTRL_OM_MASK 0x07U
#define TMR0_CTRL_OM_BITNUM 0x00U
#define TMR0_CTRL_SCS_MASK 0x0180U
#define TMR0_CTRL_SCS_BITNUM 0x07U
#define TMR0_CTRL_PCS_MASK 0x1E00U
#define TMR0_CTRL_PCS_BITNUM 0x09U
#define TMR0_CTRL_CM_MASK 0xE000U
#define TMR0_CTRL_CM_BITNUM 0x0DU
#define TMR0_CTRL *((volatile word *)0x0000F006)
/*** TMR0_SCR - Timer Channel 0 Status and Control Register; 0x0000F007 ***/
union {
word Word;
} TMR0_SCR_STR;
#define TMR0_SCR_OEN_MASK 0x01U
#define TMR0_SCR_OPS_MASK 0x02U
#define TMR0_SCR_FORCE_MASK 0x04U
#define TMR0_SCR_VAL_MASK 0x08U
#define TMR0_SCR_EEOF_MASK 0x10U
#define TMR0_SCR_MSTR_MASK 0x20U
#define TMR0_SCR_Capture_Mode0_MASK 0x40U
#define TMR0_SCR_Capture_Mode1_MASK 0x80U
#define TMR0_SCR_INPUT_MASK 0x0100U
#define TMR0_SCR_IPS_MASK 0x0200U
#define TMR0_SCR_IEFIE_MASK 0x0400U
#define TMR0_SCR_IEF_MASK 0x0800U
#define TMR0_SCR_TOFIE_MASK 0x1000U
#define TMR0_SCR_TOF_MASK 0x2000U
#define TMR0_SCR_TCFIE_MASK 0x4000U
#define TMR0_SCR_TCF_MASK 0x8000U
#define TMR0_SCR_Capture_Mode_MASK 0xC0U
#define TMR0_SCR_Capture_Mode_BITNUM 0x06U
#define TMR0_SCR *((volatile word *)0x0000F007)
/*** TMR0_CMPLD1 - Timer Channel 0 Comparator Load Register 1; 0x0000F008 ***/
union {
word Word;
} TMR0_CMPLD1_STR;
#define TMR0_CMPLD1_COMPARATOR_LOAD_10_MASK 0x01U
#define TMR0_CMPLD1_COMPARATOR_LOAD_11_MASK 0x02U
#define TMR0_CMPLD1_COMPARATOR_LOAD_12_MASK 0x04U
#define TMR0_CMPLD1_COMPARATOR_LOAD_13_MASK 0x08U
#define TMR0_CMPLD1_COMPARATOR_LOAD_14_MASK 0x10U
#define TMR0_CMPLD1_COMPARATOR_LOAD_15_MASK 0x20U
#define TMR0_CMPLD1_COMPARATOR_LOAD_16_MASK 0x40U
#define TMR0_CMPLD1_COMPARATOR_LOAD_17_MASK 0x80U
#define TMR0_CMPLD1_COMPARATOR_LOAD_18_MASK 0x0100U
#define TMR0_CMPLD1_COMPARATOR_LOAD_19_MASK 0x0200U
#define TMR0_CMPLD1_COMPARATOR_LOAD_110_MASK 0x0400U
#define TMR0_CMPLD1_COMPARATOR_LOAD_111_MASK 0x0800U
#define TMR0_CMPLD1_COMPARATOR_LOAD_112_MASK 0x1000U
#define TMR0_CMPLD1_COMPARATOR_LOAD_113_MASK 0x2000U
#define TMR0_CMPLD1_COMPARATOR_LOAD_114_MASK 0x4000U
#define TMR0_CMPLD1_COMPARATOR_LOAD_115_MASK 0x8000U
#define TMR0_CMPLD1 *((volatile word *)0x0000F008)
/*** TMR0_CMPLD2 - Timer Channel 0 Comparator Load Register 2; 0x0000F009 ***/
union {
word Word;
} TMR0_CMPLD2_STR;
#define TMR0_CMPLD2_COMPARATOR_LOAD_20_MASK 0x01U
#define TMR0_CMPLD2_COMPARATOR_LOAD_21_MASK 0x02U
#define TMR0_CMPLD2_COMPARATOR_LOAD_22_MASK 0x04U
#define TMR0_CMPLD2_COMPARATOR_LOAD_23_MASK 0x08U
#define TMR0_CMPLD2_COMPARATOR_LOAD_24_MASK 0x10U
#define TMR0_CMPLD2_COMPARATOR_LOAD_25_MASK 0x20U
#define TMR0_CMPLD2_COMPARATOR_LOAD_26_MASK 0x40U
#define TMR0_CMPLD2_COMPARATOR_LOAD_27_MASK 0x80U
#define TMR0_CMPLD2_COMPARATOR_LOAD_28_MASK 0x0100U
#define TMR0_CMPLD2_COMPARATOR_LOAD_29_MASK 0x0200U
#define TMR0_CMPLD2_COMPARATOR_LOAD_210_MASK 0x0400U
#define TMR0_CMPLD2_COMPARATOR_LOAD_211_MASK 0x0800U
#define TMR0_CMPLD2_COMPARATOR_LOAD_212_MASK 0x1000U
#define TMR0_CMPLD2_COMPARATOR_LOAD_213_MASK 0x2000U
#define TMR0_CMPLD2_COMPARATOR_LOAD_214_MASK 0x4000U
#define TMR0_CMPLD2_COMPARATOR_LOAD_215_MASK 0x8000U
#define TMR0_CMPLD2 *((volatile word *)0x0000F009)
/*** TMR0_COMSCR - Timer Channel 0 Comparator Status and Control Register; 0x0000F00A ***/
union {
word Word;
} TMR0_COMSCR_STR;
#define TMR0_COMSCR_CL10_MASK 0x01U
#define TMR0_COMSCR_CL11_MASK 0x02U
#define TMR0_COMSCR_CL20_MASK 0x04U
#define TMR0_COMSCR_CL21_MASK 0x08U
#define TMR0_COMSCR_TCF1_MASK 0x10U
#define TMR0_COMSCR_TCF2_MASK 0x20U
#define TMR0_COMSCR_TCF1EN_MASK 0x40U
#define TMR0_COMSCR_TCF2EN_MASK 0x80U
#define TMR0_COMSCR_DBG_EN0_MASK 0x4000U
#define TMR0_COMSCR_DBG_EN1_MASK 0x8000U
#define TMR0_COMSCR_CL1_MASK 0x03U
#define TMR0_COMSCR_CL1_BITNUM 0x00U
#define TMR0_COMSCR_CL2_MASK 0x0CU
#define TMR0_COMSCR_CL2_BITNUM 0x02U
#define TMR0_COMSCR_TCF_1_MASK 0x30U
#define TMR0_COMSCR_TCF_1_BITNUM 0x04U
#define TMR0_COMSCR_DBG_EN_MASK 0xC000U
#define TMR0_COMSCR_DBG_EN_BITNUM 0x0EU
#define TMR0_COMSCR *((volatile word *)0x0000F00A)
word Reserved0[5]; /* Reserved (unused) registers */
} TMR0_PRPH;
/******************************************
*** Peripheral TMR1
*******************************************/
typedef volatile struct {
/*** TMR1_CMP1 - Timer Channel 1 Compare Register #1; 0x0000F010 ***/
union {
word Word;
} TMR1_CMP1_STR;
#define TMR1_CMP1 *((volatile word *)0x0000F010)
/*** TMR1_CMP2 - Timer Channel 1 Compare Register #2; 0x0000F011 ***/
union {
word Word;
} TMR1_CMP2_STR;
#define TMR1_CMP2 *((volatile word *)0x0000F011)
/*** TMR1_CAP - Timer Channel 1 Capture Register; 0x0000F012 ***/
union {
word Word;
} TMR1_CAP_STR;
#define TMR1_CAP *((volatile word *)0x0000F012)
/*** TMR1_LOAD - Timer Channel 1 Load Register; 0x0000F013 ***/
union {
word Word;
} TMR1_LOAD_STR;
#define TMR1_LOAD_LOAD0_MASK 0x01U
#define TMR1_LOAD_LOAD1_MASK 0x02U
#define TMR1_LOAD_LOAD2_MASK 0x04U
#define TMR1_LOAD_LOAD3_MASK 0x08U
#define TMR1_LOAD_LOAD4_MASK 0x10U
#define TMR1_LOAD_LOAD5_MASK 0x20U
#define TMR1_LOAD_LOAD6_MASK 0x40U
#define TMR1_LOAD_LOAD7_MASK 0x80U
#define TMR1_LOAD_LOAD8_MASK 0x0100U
#define TMR1_LOAD_LOAD9_MASK 0x0200U
#define TMR1_LOAD_LOAD10_MASK 0x0400U
#define TMR1_LOAD_LOAD11_MASK 0x0800U
#define TMR1_LOAD_LOAD12_MASK 0x1000U
#define TMR1_LOAD_LOAD13_MASK 0x2000U
#define TMR1_LOAD_LOAD14_MASK 0x4000U
#define TMR1_LOAD_LOAD15_MASK 0x8000U
#define TMR1_LOAD *((volatile word *)0x0000F013)
/*** TMR1_HOLD - Timer Channel 1 Hold Register; 0x0000F014 ***/
union {
word Word;
} TMR1_HOLD_STR;
#define TMR1_HOLD_HOLD0_MASK 0x01U
#define TMR1_HOLD_HOLD1_MASK 0x02U
#define TMR1_HOLD_HOLD2_MASK 0x04U
#define TMR1_HOLD_HOLD3_MASK 0x08U
#define TMR1_HOLD_HOLD4_MASK 0x10U
#define TMR1_HOLD_HOLD5_MASK 0x20U
#define TMR1_HOLD_HOLD6_MASK 0x40U
#define TMR1_HOLD_HOLD7_MASK 0x80U
#define TMR1_HOLD_HOLD8_MASK 0x0100U
#define TMR1_HOLD_HOLD9_MASK 0x0200U
#define TMR1_HOLD_HOLD10_MASK 0x0400U
#define TMR1_HOLD_HOLD11_MASK 0x0800U
#define TMR1_HOLD_HOLD12_MASK 0x1000U
#define TMR1_HOLD_HOLD13_MASK 0x2000U
#define TMR1_HOLD_HOLD14_MASK 0x4000U
#define TMR1_HOLD_HOLD15_MASK 0x8000U
#define TMR1_HOLD *((volatile word *)0x0000F014)
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