qtimer_2.c

菲斯卡尔无传感器无刷控制方案。具体说明文档和程序都在压缩包内。

/** ###################################################################
**     THIS BEAN MODULE IS GENERATED BY THE TOOL. DO NOT MODIFY IT.
**     Filename  : QTIMER_2.C
**     Project   : bldc_zc_8013
**     Processor : 56F8013VFAE
**     Beantype  : Init_TMR
**     Version   : Bean 01.100, Driver 01.15, CPU db: 2.87.068
**     Compiler  : Metrowerks DSP C Compiler
**     Date/Time : 23.5.2005, 11:21
**     Abstract  :
**         This "Init_TMR" Peripheral Inspector implements the
**         Quad Timer module (TMR), basic initialization
**         and settings.
**     Settings  :
**         Timer counter device        : TMR2
**
**         Operation mode              : Count mode
**         Count once                  : count repeatedly
**         Count length                : count till compare, then reinitialize
**         Count direction             : up
**         Master mode                 : Disabled
**         External OFLAG force        : Disabled
**         Forced OFLAG value          : Disabled
**         Force OFLAG ouput           : Disabled
**         Output enable               : no
**         Output polarity             : true
**         Input  polarity             : true
**         Co-channel init.            : Disabled
**
**         Primary source              : prescaler (IP BUS clock)
**         Secondary source            : counter 2 input pin
**
**         Input capture mode          : Disabled
**
**         Output mode                 : asserted while counter is active
**
**         Compare load control 1      : Disabled
**         Compare load control 2      : Disabled
**
**         Debug mode action           : Normal operation
**
**         Interrupts
**             Timer compare           : Enabled
**             Timer overflow          : Disabled
**             Input edge              : Disabled
**             Timer compare 1         : Disabled
**             Timer compare 2         : Disabled
**             ISR name                : IsrSpeedCurrentControl
**             Interrupt name          : INT_TMR2
**             Priority                : 1
**     Contents  :
**         Init - void QTIMER_2_Init(void);
**
**     (c) Copyright UNIS, spol. s r.o. 1997-2004
**     UNIS, spol. s r.o.
**     Jundrovska 33
**     624 00 Brno
**     Czech Republic
**     http      : www.processorexpert.com
**     mail      : [e-mail]
** ###################################################################*/

/* MODULE QTIMER_2. */

#include "QTIMER_2.h"

/*
** ###################################################################
**
**  The following method must be implemented by the user in one
**  of the following modules:
**
**    #pragma interrupt
**    void IsrSpeedCurrentControl(void)
**
**  Modules:
**       bldc_zc_8013
**
** ###################################################################
*/

/*
** ===================================================================
**     Method      :  QTIMER_2_Init (bean Init_TMR)
**
**     Description :
**         This method initializes registers of the TMR module
**         according to this Peripheral Initialization Bean settings.
**         Call this method in the user code to initialize the
**         module. By default, the method is called by PE
**         automatically; see "Call Init method" property of the
**         bean for more details.
**     Parameters  : None
**     Returns     : Nothing
** ===================================================================
*/
void QTIMER_2_Init(void)
{
  setReg16(TMR2_CMP1,C_QTIMER_2_reg_TMR2_CMP1); /* Set the Compare register 1 */ 
  setReg16(TMR2_CMP2,C_QTIMER_2_reg_TMR2_CMP2); /* Set the Compare register 2 */ 
  setReg16(TMR2_LOAD,C_QTIMER_2_reg_TMR2_LOAD); /* Set the Load register */ 
  setReg16(TMR2_CNTR,C_QTIMER_2_reg_TMR2_CNTR); /* Set the Counter register */ 
  /* TMR2_SCR: TCF=0,TCFIE=1,TOF=0,TOFIE=0,IEF=0,IEFIE=0,IPS=0,INPUT=0,Capture_Mode=0,MSTR=0,EEOF=0,VAL=0,FORCE=0,OPS=0,OEN=0 */
  setReg16(TMR2_SCR,C_QTIMER_2_reg_TMR2_SCR); /* Set the Status and control register */ 
  /* TMR2_CMPLD1: COMPARATOR_LOAD_1=0 */
  setReg16(TMR2_CMPLD1,C_QTIMER_2_reg_TMR2_CMPLD1); /* Set the Comparator load register 1 */ 
  /* TMR2_CMPLD2: COMPARATOR_LOAD_2=0 */
  setReg16(TMR2_CMPLD2,C_QTIMER_2_reg_TMR2_CMPLD2); /* Set the Comparator load register 2 */ 
  /* TMR2_COMSCR: DBG_EN=0,??=0,??=0,??=0,??=0,??=0,??=0,TCF2EN=0,TCF1EN=0,TCF2=0,TCF1=0,CL2=0,CL1=0 */
  setReg16(TMR2_COMSCR,C_QTIMER_2_reg_TMR2_COMSCR); /* Set the Comparator status/control register */ 
  /* TMR2_CTRL: CM=1,PCS=8,SCS=2,ONCE=0,LENGTH=1,DIR=0,Co_INIT=0,OM=0 */
  setReg16(TMR2_CTRL,C_QTIMER_2_reg_TMR2_CTRL); /* Set the Control register */ 
}

/* END QTIMER_2. */

/*
** ###################################################################
**
**     This file was created by UNIS Processor Expert 2.96 [03.65]
**     for the Freescale 56800 series of microcontrollers.
**
** ###################################################################
*/