smc9218.h

一个DSP_TCPIP 协议栈网络驱动的例子

 c--;\
}\
}while(0)
#else
#define SMC_outsl(a,r,p,l) do\
{\
unsigned int *ptr = p;\
unsigned int c = l;\
while(c)\
{\
*((unsigned int*)(a+r)) = *ptr;\
ptr++;\
c--;\
}\
}while(0)
#endif
#endif

#ifdef USE_DMA
#define SMC_insl(a,r,p,l) do\
{\
unsigned char *dma_addr = (unsigned char*)0x808000; \
*dma_addr = 0xd40; \
*(dma_addr + 4) = (unsigned char)(a+r);\
*(dma_addr + 6) = (unsigned char)dma_rx_buff; \
*(dma_addr + 8) = l; \
*dma_addr = 0xd43;\
}while(0)
#else
#ifndef _PLATFORM_8_BIT
#define SMC_insl(a,r,p,l)  do\
{\
 unsigned char *ptr = p;\
 unsigned char dd;\
 unsigned char c = l;\
 while(c)\
    {\
    dd = *((volatile unsigned int*)(a+r));\
    *ptr++ = dd & 0xff;\
    *ptr++ = (dd >> 8) & 0xff;\
    *ptr++ = (dd >> 16) & 0xff;\
    *ptr++ = (dd >> 24) & 0xff;\
    c -= 1;\
    }\
    }while(0)
#else
#define SMC_insl(a,r,p,l) do\
{\
 unsigned int *ptr = p;\
 unsigned int c = l;\
 while(c)\
    {\
    *ptr ++ = *((volatile unsigned int*)(a+r));\
    c -= 1;\
    }\
}while(0)
#endif
#endif
#define SMC_outl(x,a,r) *((volatile unsigned int*)(a+r)) = x
#define SMC_inl(a,r) *((volatile unsigned int*)(a+r))
/* FIFO read/write macros */
#define SMC_PUSH_DATA(p, l) SMC_outsl( ioaddr, TX_DATA_FIFO, p, (l) >> 2 ) /* 写缓冲区 */
#define SMC_PULL_DATA(p, l) SMC_insl ( ioaddr, RX_DATA_FIFO, p, (l) >> 2 ) /* 读缓冲区 */
#define SMC_SET_TX_FIFO(x)  SMC_outl( x, ioaddr, TX_DATA_FIFO ) /* comment */
#define SMC_GET_RX_FIFO()   SMC_inl( ioaddr, RX_DATA_FIFO ) /* comment */

/* I/O mapped register read/write macros */
#define SMC_GET_TX_STS_FIFO()       SMC_inl( ioaddr, TX_STATUS_FIFO ) /* comment */
#define SMC_GET_RX_STS_FIFO()       SMC_inl( ioaddr, RX_STATUS_FIFO ) /* comment */
#define SMC_GET_RX_STS_FIFO_PEEK()  SMC_inl( ioaddr, RX_STATUS_FIFO_PEEK ) /* comment */
#define SMC_GET_PN()            (SMC_inl( ioaddr, ID_REV ) >> 16) /* comment */
#define SMC_GET_REV()           (SMC_inl( ioaddr, ID_REV ) & 0xFFFF) /* comment */
#define SMC_GET_IRQ_CFG()       SMC_inl( ioaddr, INT_CFG ) /* comment */
#define SMC_SET_IRQ_CFG(x)      SMC_outl( x, ioaddr, INT_CFG ) /* comment */
#define SMC_GET_INT()           SMC_inl( ioaddr, INT_STS )
#define SMC_ACK_INT(x)          SMC_outl( x, ioaddr, INT_STS ) /* comment */
#define SMC_GET_INT_EN()        SMC_inl( ioaddr, INT_EN ) /* comment */
#define SMC_SET_INT_EN(x)       SMC_outl( x, ioaddr, INT_EN ) /* comment */
#define SMC_GET_BYTE_TEST()     SMC_inl( ioaddr, BYTE_TEST ) /* comment */
#define SMC_SET_BYTE_TEST(x)        SMC_outl( x, ioaddr, BYTE_TEST ) /* comment */
#define SMC_GET_FIFO_INT()      SMC_inl( ioaddr, FIFO_INT ) /* comment */
#define SMC_SET_FIFO_INT(x)     SMC_outl( x, ioaddr, FIFO_INT ) /* comment */
#define SMC_SET_FIFO_TDA(x)                 \
    do {                            \
        int __mask;                 \
        __mask = SMC_GET_FIFO_INT() & ~(0xFF<<24); /* mask */ \
        SMC_SET_FIFO_INT( __mask | (x)<<24 ); /* mask */      \
    } while (0)
#define SMC_SET_FIFO_TSL(x)                 \
    do {                            \
        int __mask;                 \
        __mask = SMC_GET_FIFO_INT() & ~(0xFF<<16); /* mask */ \
        SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<16)); /* mask */\
    } while (0)
#define SMC_SET_FIFO_RSA(x)                 \
    do {                            \
        int __mask;                 \
        __mask = SMC_GET_FIFO_INT() & ~(0xFF<<8); /* mask */  \
        SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<8)); /* mask */ \
    } while (0)
#define SMC_SET_FIFO_RSL(x)                 \
    do {                            \
        int __mask;                 \
        __mask = SMC_GET_FIFO_INT() & ~0xFF; /* mask */       \
        SMC_SET_FIFO_INT( __mask | ((x) & 0xFF)); /* mask */   \
    } while (0)

#define SMC_GET_RX_CFG()        SMC_inl( ioaddr, RX_CFG ) /* comment */
#define SMC_SET_RX_CFG(x)       SMC_outl( x, ioaddr, RX_CFG ) /* comment */
#define SMC_GET_TX_CFG()        SMC_inl( ioaddr, TX_CFG ) /* comment */
#define SMC_SET_TX_CFG(x)       SMC_outl( x, ioaddr, TX_CFG ) /* comment */
#define SMC_GET_HW_CFG()        SMC_inl( ioaddr, HW_CFG ) /* comment */
#define SMC_SET_HW_CFG(x)       SMC_outl( x, ioaddr, HW_CFG ) /* comment */
#define SMC_GET_RX_DP_CTRL()    SMC_inl( ioaddr, RX_DP_CTRL ) /* comment */
#define SMC_SET_RX_DP_CTRL(x)   SMC_outl( x, ioaddr, RX_DP_CTRL ) /* comment */
#define SMC_GET_PMT_CTRL()      SMC_inl( ioaddr, PMT_CTRL ) /* comment */
#define SMC_SET_PMT_CTRL(x)     SMC_outl( x, ioaddr, PMT_CTRL ) /* comment */
#define SMC_GET_GPIO_CFG()      SMC_inl( ioaddr, GPIO_CFG ) /* comment */
#define SMC_SET_GPIO_CFG(x)     SMC_outl( x, ioaddr, GPIO_CFG ) /* comment */
#define SMC_GET_RX_FIFO_INF()   SMC_inl( ioaddr, RX_FIFO_INF ) /* comment */
#define SMC_SET_RX_FIFO_INF(x)  SMC_outl( x, ioaddr, RX_FIFO_INF ) /* comment */
#define SMC_GET_TX_FIFO_INF()   SMC_inl( ioaddr, TX_FIFO_INF ) /* comment */
#define SMC_SET_TX_FIFO_INF(x)  SMC_outl( x, ioaddr, TX_FIFO_INF ) /* comment */
#define SMC_GET_GPT_CFG()       SMC_inl( ioaddr, GPT_CFG ) /* comment */
#define SMC_SET_GPT_CFG(x)      SMC_outl( x, ioaddr, GPT_CFG ) /* comment */
#define SMC_GET_RX_DROP()       SMC_inl( ioaddr, RX_DROP ) /* comment */
#define SMC_SET_RX_DROP(x)      SMC_outl( x, ioaddr, RX_DROP ) /* comment */
#define SMC_GET_MAC_CMD()       SMC_inl( ioaddr, MAC_CSR_CMD ) /* comment */
#define SMC_SET_MAC_CMD(x)      SMC_outl( x, ioaddr, MAC_CSR_CMD ) /* comment */
#define SMC_GET_MAC_DATA()      SMC_inl( ioaddr, MAC_CSR_DATA ) /* comment */
#define SMC_SET_MAC_DATA(x)     SMC_outl( x, ioaddr, MAC_CSR_DATA ) /* comment */
#define SMC_GET_AFC_CFG()       SMC_inl( ioaddr, AFC_CFG ) /* comment */
#define SMC_SET_AFC_CFG(x)      SMC_outl( x, ioaddr, AFC_CFG ) /* comment */

/* MAC register read/write macros */
#define SMC_GET_MAC_CSR(a,v)                        \
    do {                                \
        while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_);  \
        SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ |         \
            MAC_CSR_CMD_R_NOT_W_ | (a) );           \
        while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_);  \
        v = SMC_GET_MAC_DATA();                 \
    } while (0)
#define SMC_SET_MAC_CSR(a,v)                        \
    do {                                \
        while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_);  \
        SMC_SET_MAC_DATA(v);                    \
        SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | (a) );      \
        while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_);  \
    } while (0)
#define SMC_GET_MAC_CR(x)   SMC_GET_MAC_CSR( MAC_CR, x ) /* comment */
#define SMC_SET_MAC_CR(x)   SMC_SET_MAC_CSR( MAC_CR, x ) /* comment */
#define SMC_GET_ADDRH(x)    SMC_GET_MAC_CSR( ADDRH, x ) /* comment */
#define SMC_SET_ADDRH(x)    SMC_SET_MAC_CSR( ADDRH, x ) /* comment */
#define SMC_GET_ADDRL(x)    SMC_GET_MAC_CSR( ADDRL, x ) /* comment */
#define SMC_SET_ADDRL(x)    SMC_SET_MAC_CSR( ADDRL, x ) /* comment */
#define SMC_GET_HASHH(x)    SMC_GET_MAC_CSR( HASHH, x ) /* comment */
#define SMC_SET_HASHH(x)    SMC_SET_MAC_CSR( HASHH, x ) /* comment */
#define SMC_GET_HASHL(x)    SMC_GET_MAC_CSR( HASHL, x ) /* comment */
#define SMC_SET_HASHL(x)    SMC_SET_MAC_CSR( HASHL, x ) /* comment */
#define SMC_GET_MII_ACC(x)  SMC_GET_MAC_CSR( MII_ACC, x ) /* comment */
#define SMC_SET_MII_ACC(x)  SMC_SET_MAC_CSR( MII_ACC, x ) /* comment */
#define SMC_GET_MII_DATA(x) SMC_GET_MAC_CSR( MII_DATA, x ) /* comment */
#define SMC_SET_MII_DATA(x) SMC_SET_MAC_CSR( MII_DATA, x ) /* comment */
#define SMC_GET_FLOW(x)     SMC_GET_MAC_CSR( FLOW, x ) /* comment */
#define SMC_SET_FLOW(x)     SMC_SET_MAC_CSR( FLOW, x ) /* comment */
#define SMC_GET_VLAN1(x)    SMC_GET_MAC_CSR( VLAN1, x ) /* comment */
#define SMC_SET_VLAN1(x)    SMC_SET_MAC_CSR( VLAN1, x ) /* comment */
#define SMC_GET_VLAN2(x)    SMC_GET_MAC_CSR( VLAN2, x ) /* comment */
#define SMC_SET_VLAN2(x)    SMC_SET_MAC_CSR( VLAN2, x ) /* comment */
#define SMC_SET_WUFF(x)     SMC_SET_MAC_CSR( WUFF, x ) /* comment */
#define SMC_GET_WUCSR(x)    SMC_GET_MAC_CSR( WUCSR, x ) /* comment */
#define SMC_SET_WUCSR(x)    SMC_SET_MAC_CSR( WUCSR, x ) /* comment */

/* PHY register read/write macros */
#define SMC_GET_MII(a,phy,v)                    \
    do {                            \
        unsigned int __v;                   \
        do {                        \
            SMC_GET_MII_ACC(__v);           \
        } while ( __v & MII_ACC_MII_BUSY_ );        \
        SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) |   /* mask */\
            MII_ACC_MII_BUSY_);         \
        do {                        \
            SMC_GET_MII_ACC(__v);           \
        } while ( __v & MII_ACC_MII_BUSY_ );        \
        SMC_GET_MII_DATA(v);                \
    } while (0)
#define SMC_SET_MII(a,phy,v)                   \
    do {                            \
        unsigned int __v;                   \
        do {                        \
            SMC_GET_MII_ACC(__v);           \
        } while ( __v & MII_ACC_MII_BUSY_ );        \
        SMC_SET_MII_DATA(v);                \
        SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) |   /* mask */\
            MII_ACC_MII_BUSY_    |      \
            MII_ACC_MII_WRITE_  );          \
        do {                        \
            SMC_GET_MII_ACC(__v);           \
        } while ( __v & MII_ACC_MII_BUSY_ );        \
    } while (0)

#define SMC_GET_PHY_BMCR(phy,x)     SMC_GET_MII( MII_BMCR, phy, x ) /* comment */
#define SMC_SET_PHY_BMCR(phy,x)     SMC_SET_MII( MII_BMCR, phy, x ) /* comment */
#define SMC_GET_PHY_BMSR(phy,x)     SMC_GET_MII( MII_BMSR, phy, x ) /* comment */
#define SMC_GET_PHY_ID1(phy,x)      SMC_GET_MII( MII_PHYSID1, phy, x ) /* comment */
#define SMC_GET_PHY_ID2(phy,x)      SMC_GET_MII( MII_PHYSID2, phy, x ) /* comment */
#define SMC_GET_PHY_MII_ADV(phy,x)  SMC_GET_MII( MII_ADVERTISE, phy, x ) /* comment */
#define SMC_SET_PHY_MII_ADV(phy,x)  SMC_SET_MII( MII_ADVERTISE, phy, x ) /* comment */
#define SMC_GET_PHY_MII_LPA(phy,x)  SMC_GET_MII( MII_LPA, phy, x ) /* comment */
#define SMC_SET_PHY_MII_LPA(phy,x)  SMC_SET_MII( MII_LPA, phy, x ) /* comment */
#define SMC_GET_PHY_CTRL_STS(phy,x) SMC_GET_MII( PHY_MODE_CTRL_STS, phy, x ) /* comment */
#define SMC_SET_PHY_CTRL_STS(phy,x) SMC_SET_MII( PHY_MODE_CTRL_STS, phy, x ) /* comment */
#define SMC_GET_PHY_INT_SRC(phy,x)  SMC_GET_MII( PHY_INT_SRC, phy, x ) /* comment */
#define SMC_SET_PHY_INT_SRC(phy,x)  SMC_SET_MII( PHY_INT_SRC, phy, x ) /* comment */
#define SMC_GET_PHY_INT_MASK(phy,x) SMC_GET_MII( PHY_INT_MASK, phy, x ) /* comment */
#define SMC_SET_PHY_INT_MASK(phy,x) SMC_SET_MII( PHY_INT_MASK, phy, x ) /* comment */
#define SMC_GET_PHY_SPECIAL(phy,x)  SMC_GET_MII( PHY_SPECIAL, phy, x ) /* comment */

#ifndef SMC_GET_MAC_ADDR
#define SMC_GET_MAC_ADDR(addr)                  \
    do {                            \
        unsigned int __v;               \
                                \
        SMC_GET_MAC_CSR(ADDRL, __v);            \
        addr[0] = __v; addr[1] = __v >> 8;    /* mask */  \
        addr[2] = __v >> 16; addr[3] = __v >> 24;  /* mask */ \
        SMC_GET_MAC_CSR(ADDRH, __v);            \
        addr[4] = __v; addr[5] = __v >> 8;  /* mask */    \
    } while (0)
#endif

#define SMC_SET_MAC_ADDR(addr)                  \
    do {                            \
         SMC_SET_MAC_CSR(ADDRL,             \
                 addr[0] |       /* mask */   \
                (addr[1] << 8) |     /* mask */   \
                (addr[2] << 16) | /* mask */      \
                (addr[3] << 24));  /* mask */     \
         SMC_SET_MAC_CSR(ADDRH, addr[4]|(addr[5] << 8));/* mask */\
    } while (0)

#ifdef USE_DMA
void smc9218_dma( void );
#endif

#endif