📄 smc9218.h
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#define INT_EN_GPIO2_INT_ (0x00000004) /* R/W */
#define INT_EN_GPIO1_INT_ (0x00000002) /* R/W */
#define INT_EN_GPIO0_INT_ (0x00000001) /* R/W */
#define BYTE_TEST (0x64 >> SMC9218_BUS_OFF) /* byte order test register */
#define FIFO_INT (0x68 >> SMC9218_BUS_OFF) /* fifo level interrupt */
#define FIFO_INT_TX_AVAIL_LEVEL_ (0xFF000000) /* R/W */
#define FIFO_INT_TX_STS_LEVEL_ (0x00FF0000) /* R/W */
#define FIFO_INT_RX_AVAIL_LEVEL_ (0x0000FF00) /* R/W */
#define FIFO_INT_RX_STS_LEVEL_ (0x000000FF) /* R/W */
#define RX_CFG (0x6C >> SMC9218_BUS_OFF) /* receiver configuration register */
#define RX_CFG_RX_END_ALGN_ (0xC0000000) /* R/W */
#define RX_CFG_RX_END_ALGN4_ (0x00000000) /* R/W */
#define RX_CFG_RX_END_ALGN16_ (0x40000000) /* R/W */
#define RX_CFG_RX_END_ALGN32_ (0x80000000) /* R/W */
#define RX_CFG_RX_DMA_CNT_ (0x0FFF0000) /* R/W */
#define RX_CFG_RX_DUMP_ (0x00008000) /* R/W */
#define RX_CFG_RXDOFF_ (0x00001F00) /* R/W */
#define TX_CFG (0x70 >> SMC9218_BUS_OFF) /* transmit configuration register */
#define TX_CFG_TXS_DUMP_ (0x00008000) /* Self Clearing */
#define TX_CFG_TXD_DUMP_ (0x00004000) /* Self Clearing */
#define TX_CFG_TXSAO_ (0x00000004) /* R/W */
#define TX_CFG_TX_ON_ (0x00000002) /* R/W */
#define TX_CFG_STOP_TX_ (0x00000001) /* Self Clearing */
#define HW_CFG (0x74 >> SMC9218_BUS_OFF) /* hardware configuration register */
#define HW_CFG_TTM_ (0x00200000) /* R/W */
#define HW_CFG_SF_ (0x00100000) /* R/W */
#define HW_CFG_TX_FIF_SZ_ (0x000F0000) /* R/W */
#define HW_CFG_TR_ (0x00003000) /* R/W */
#define HW_CFG_PHY_CLK_SEL_ (0x00000060) /* R/W */
#define HW_CFG_PHY_CLK_SEL_INT_PHY_ (0x00000000) /* R/W */
#define HW_CFG_PHY_CLK_SEL_EXT_PHY_ (0x00000020) /* R/W */
#define HW_CFG_PHY_CLK_SEL_CLK_DIS_ (0x00000040) /* R/W */
#define HW_CFG_SMI_SEL_ (0x00000010) /* R/W */
#define HW_CFG_EXT_PHY_DET_ (0x00000008) /* RO */
#define HW_CFG_EXT_PHY_EN_ (0x00000004) /* R/W */
#define HW_CFG_32_16_BIT_MODE_ (0x00000004) /* RO */
#define HW_CFG_SRST_TO_ (0x00000002) /* RO */
#define HW_CFG_SRST_ (0x00000001) /* Self Clearing */
#define RX_DP_CTRL (0x78 >> SMC9218_BUS_OFF) /* receive datapath control register */
#define RX_DP_CTRL_RX_FFWD_ (0x80000000) /* R/W */
#define RX_DP_CTRL_FFWD_BUSY_ (0x80000000) /* ??? */
#define RX_FIFO_INF (0x7C >> SMC9218_BUS_OFF) /* receive fifo information register */
#define RX_FIFO_INF_RXSUSED_ (0x00FF0000) /* RO */
#define RX_FIFO_INF_RXDUSED_ (0x0000FFFF) /* RO */
#define TX_FIFO_INF (0x80 >> SMC9218_BUS_OFF) /* transmit fifo information register */
#define TX_FIFO_INF_TSUSED_ (0x00FF0000) /* RO */
#define TX_FIFO_INF_TDFREE_ (0x0000FFFF) /* RO */
#define PMT_CTRL (0x84 >> SMC9218_BUS_OFF) /* power managment control register */
#define PMT_CTRL_PM_MODE_ (0x00003000) /* Self Clearing */
#define PMT_CTRL_PHY_RST_ (0x00000400) /* Self Clearing */
#define PMT_CTRL_WOL_EN_ (0x00000200) /* R/W */
#define PMT_CTRL_ED_EN_ (0x00000100) /* R/W */
#define PMT_CTRL_PME_TYPE_ (0x00000040) /* R/W Not Affected by SW Reset */
#define PMT_CTRL_WUPS_ (0x00000030) /* R/WC */
#define PMT_CTRL_WUPS_NOWAKE_ (0x00000000) /* R/WC */
#define PMT_CTRL_WUPS_ED_ (0x00000010) /* R/WC */
#define PMT_CTRL_WUPS_WOL_ (0x00000020) /* R/WC */
#define PMT_CTRL_WUPS_MULTI_ (0x00000030) /* R/WC */
#define PMT_CTRL_PME_IND_ (0x00000008) /* R/W */
#define PMT_CTRL_PME_POL_ (0x00000004) /* R/W */
#define PMT_CTRL_PME_EN_ (0x00000002) /* R/W Not Affected by SW Reset */
#define PMT_CTRL_READY_ (0x00000001) /* RO */
#define GPIO_CFG (0x88 >> SMC9218_BUS_OFF) /* general purpose io configuration register*/
#define GPIO_CFG_LED3_EN_ (0x40000000) /* R/W */
#define GPIO_CFG_LED2_EN_ (0x20000000) /* R/W */
#define GPIO_CFG_LED1_EN_ (0x10000000) /* R/W */
#define GPIO_CFG_GPIO2_INT_POL_ (0x04000000) /* R/W */
#define GPIO_CFG_GPIO1_INT_POL_ (0x02000000) /* R/W */
#define GPIO_CFG_GPIO0_INT_POL_ (0x01000000) /* R/W */
#define GPIO_CFG_EEPR_EN_ (0x00700000) /* R/W */
#define GPIO_CFG_GPIOBUF2_ (0x00040000) /* R/W */
#define GPIO_CFG_GPIOBUF1_ (0x00020000) /* R/W */
#define GPIO_CFG_GPIOBUF0_ (0x00010000) /* R/W */
#define GPIO_CFG_GPIODIR2_ (0x00000400) /* R/W */
#define GPIO_CFG_GPIODIR1_ (0x00000200) /* R/W */
#define GPIO_CFG_GPIODIR0_ (0x00000100) /* R/W */
#define GPIO_CFG_GPIOD4_ (0x00000010) /* R/W */
#define GPIO_CFG_GPIOD3_ (0x00000008) /* R/W */
#define GPIO_CFG_GPIOD2_ (0x00000004) /* R/W */
#define GPIO_CFG_GPIOD1_ (0x00000002) /* R/W */
#define GPIO_CFG_GPIOD0_ (0x00000001) /* R/W */
#define GPT_CFG (0x8C >> SMC9218_BUS_OFF) /* general purpose timer configuration register */
#define GPT_CFG_TIMER_EN_ (0x20000000) /* R/W */
#define GPT_CFG_GPT_LOAD_ (0x0000FFFF) /* R/W */
#define GPT_CNT (0x90 >> SMC9218_BUS_OFF) /* general purpose timer current count register */
#define GPT_CNT_GPT_CNT_ (0x0000FFFF) /* RO */
#define ENDIAN (0x98 >> SMC9218_BUS_OFF) /* word swap control */
#define FREE_RUN (0x9C >> SMC9218_BUS_OFF) /* free run 25mhz counter */
#define RX_DROP (0xA0 >> SMC9218_BUS_OFF) /* receive dropped frame counter */
#define MAC_CSR_CMD (0xA4 >> SMC9218_BUS_OFF) /* mac csr synchronizer command register*/
#define MAC_CSR_CMD_CSR_BUSY_ (0x80000000) /* Self Clearing */
#define MAC_CSR_CMD_R_NOT_W_ (0x40000000) /* R/W */
#define MAC_CSR_CMD_CSR_ADDR_ (0x000000FF) /* R/W */
#define MAC_CSR_DATA (0xA8 >> SMC9218_BUS_OFF) /* mac csr synchronizer data register */
#define AFC_CFG (0xAC >> SMC9218_BUS_OFF) /* automatic flow control configruation register */
#define AFC_CFG_AFC_HI_ (0x00FF0000) /* R/W */
#define AFC_CFG_AFC_LO_ (0x0000FF00) /* R/W */
#define AFC_CFG_BACK_DUR_ (0x000000F0) /* R/W */
#define AFC_CFG_FCMULT_ (0x00000008) /* R/W */
#define AFC_CFG_FCBRD_ (0x00000004) /* R/W */
#define AFC_CFG_FCADD_ (0x00000002) /* R/W */
#define AFC_CFG_FCANY_ (0x00000001) /* R/W */
/* EEPROM 寄存器没有定义，不使用他们 */
/* end of LAN register offsets and bit definitions */
/*
****************************************************************************
****************************************************************************
* MAC Control and Status Register (Indirect Address)
* Offset (through the MAC_CSR CMD and DATA port)
****************************************************************************
****************************************************************************
*
*/
#define MAC_CR (0x01) /* mac control register */
#define MAC_CR_RXALL_ (0x80000000) /* receive all */
#define MAC_CR_RCVOWN_ (0x00800000) /* receive own */
#define MAC_CR_LOOPBK_ (0x00200000) /* loopback operation mode */
#define MAC_CR_FDPX_ (0x00100000) /* full duplex mode */
#define MAC_CR_MCPAS_ (0x00080000) /* pass all mutilcast */
#define MAC_CR_PRMS_ (0x00040000) /* promiscuous*/
#define MAC_CR_INVFILT_ (0x00020000) /* invert filtering */
#define MAC_CR_PASSBAD_ (0x00010000) /* pass bad frame */
#define MAC_CR_HFILT_ (0x00008000) /* hash only filtering mode */
#define MAC_CR_HPFILT_ (0x00002000) /* hash perfect filtering mode */
#define MAC_CR_LCOLL_ (0x00001000) /* late collision control */
#define MAC_CR_BCAST_ (0x00000800) /* disable broadcast frame */
#define MAC_CR_DISRTY_ (0x00000400) /* disable retry */
#define MAC_CR_PADSTR_ (0x00000100) /* automatic pad stripping */
#define MAC_CR_BOLMT_MASK_ (0x000000C0) /* backoff limit */
#define MAC_CR_DFCHK_ (0x00000020) /* deferral check */
#define MAC_CR_TXEN_ (0x00000008) /* transmit enable */
#define MAC_CR_RXEN_ (0x00000004) /* receive enable */
#define ADDRH (0x02) /* R/W mask 0x0000FFFFUL */
#define ADDRL (0x03) /* R/W mask 0xFFFFFFFFUL */
#define HASHH (0x04) /* R/W */
#define HASHL (0x05) /* R/W */
#define MII_ACC (0x06) /* R/W */
#define MII_ACC_PHY_ADDR_ (0x0000F800) /* phy address */
#define MII_ACC_MIIRINDA_ (0x000007C0) /* mii register index */
#define MII_ACC_MII_WRITE_ (0x00000002) /* mii write or read */
#define MII_ACC_MII_BUSY_ (0x00000001) /* mii busy */
#define MII_DATA (0x07) /* R/W mask 0x0000FFFFUL */
#define FLOW (0x08) /* flow control register */
#define FLOW_FCPT_ (0xFFFF0000) /* pause time */
#define FLOW_FCPASS_ (0x00000004) /* pass control frame */
#define FLOW_FCEN_ (0x00000002) /* flow control enable */
#define FLOW_FCBSY_ (0x00000001) /* flow control busy */
#define VLAN1 (0x09) /* R/W mask 0x0000FFFFUL */
#define VLAN1_VTI1_ (0x0000ffff) /* VTI */
#define VLAN2 (0x0A) /* R/W mask 0x0000FFFFUL */
#define VLAN2_VTI2_ (0x0000ffff) /* VTI */
#define WUFF (0x0B) /* wake up frame filter */
#define WUCSR (0x0C) /* wake up control and status register */
#define WUCSR_GUE_ (0x00000200) /* global unicast enable */
#define WUCSR_WUFR_ (0x00000040) /* remote wake-up frame received */
#define WUCSR_MPR_ (0x00000020) /* magic packet received */
#define WUCSR_WAKE_EN_ (0x00000004) /* wake-up frame enable */
#define WUCSR_MPEN_ (0x00000002) /* magic packet enable */
/*
****************************************************************************
* Chip Specific MII Defines
****************************************************************************
*
* Phy register offsets and bit definitions
*
*/
#define PHY_MODE_CTRL_STS (17) /* Mode Control/Status Register */
#define MODE_CTRL_STS_EDPWRDOWN_ (0x2000) /* power down dectected */
#define MODE_CTRL_STS_ENERGYON_ (0x0002) /* energy is dectected*/
#define PHY_INT_SRC (29) /* interrupt source flag */
#define PHY_INT_SRC_ENERGY_ON_ (0x0080) /* energy on */
#define PHY_INT_SRC_ANEG_COMP_ (0x0040) /* auto negotiation complete */
#define PHY_INT_SRC_REMOTE_FAULT_ (0x0020) /* remote fault detected */
#define PHY_INT_SRC_LINK_DOWN_ (0x0010) /* link down */
#define PHY_INT_SRC_ANEG_LP_ACK_ (0x0008) /* auto negotiation lp ack */
#define PHY_INT_SRC_PAR_DET_FAULT_ (0x0004) /* parallel detection fault */
#define PHY_INT_SRC_ANEG_PGRX_ (0x0002) /* auto negotiation page received */
#define PHY_INT_MASK (30) /* interrupt source mask */
#define PHY_INT_MASK_ENERGY_ON_ (0x0080) /* energy on */
#define PHY_INT_MASK_ANEG_COMP_ (0x0040) /* auto negotiation complete */
#define PHY_INT_MASK_REMOTE_FAULT_ (0x0020) /* remote fault detected */
#define PHY_INT_MASK_LINK_DOWN_ (0x0010) /* link down */
#define PHY_INT_MASK_ANEG_LP_ACK_ (0x0008) /* auto negotiation lp ack */
#define PHY_INT_MASK_PAR_DET_FAULT_ (0x0004) /* parallel detection fault */
#define PHY_INT_MASK_ANEG_PGRX_ (0x0002) /* auto negotiation page received */
#define PHY_SPECIAL (31) /* PHY special status/control register */
#define PHY_SPECIAL_ANEG_DONE_ (0x1000) /* auto done */
#define PHY_SPECIAL_RES_ (0x0040) /* resverd */
#define PHY_SPECIAL_RES_MASK_ (0x0FE1) /* res mask */
#define PHY_SPECIAL_SPD_ (0x001C) /* speed indication */
#define PHY_SPECIAL_SPD_10HALF_ (0x0004) /* 10M half-duplex */
#define PHY_SPECIAL_SPD_10FULL_ (0x0014) /* 10M full-duplex */
#define PHY_SPECIAL_SPD_100HALF_ (0x0008) /* 100Base-Tx half-duplex */
#define PHY_SPECIAL_SPD_100FULL_ (0x0018) /* 100Base-Tx full-duplex */
/* 寄存器读写宏 */
#ifdef USE_DMA_SEND
#define SMC_outsl(a,r,p,l) do\
{\
unsigned char *dma_addr = (unsigned char*)0x808000; \
*dma_addr = 0xc10; \
*(dma_addr + 4) = (unsigned char)p; \
*(dma_addr + 6) = (unsigned char)(a+r); \
*(dma_addr + 8) = l; \
*dma_addr = 0xc13; \
}while(0);
#else
#ifndef _PLATFORM_8_BIT
#define SMC_outsl(a,r,p,l) do\
{\
unsigned char* ptr = p;\
unsigned char c = l;\
while(c)\
{\
*((unsigned char*)a+r) = *ptr;\
ptr++;\
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