smc9218.h

一个DSP_TCPIP 协议栈网络驱动的例子

#ifndef _SMC9218_H_
#define _SMC9218_H_

#ifndef _PLATFORM_8_BIT
#define SMC9218_BUS_OFF 2
#else
#define SMC9218_BUS_OFF 0
#endif

#define IS_REV_A(x) ((x & 0xFFFF)==0) /* revsion A */
/* Generic MII registers. */

#define MII_BMCR            0x00        /* Basic mode control register */
#define MII_BMSR            0x01        /* Basic mode status register  */
#define MII_PHYSID1         0x02        /* PHYS ID 1                   */
#define MII_PHYSID2         0x03        /* PHYS ID 2                   */
#define MII_ADVERTISE       0x04        /* Advertisement control reg   */
#define MII_LPA             0x05        /* Link partner ability reg    */
#define MII_EXPANSION       0x06        /* Expansion register          */
#define MII_CTRL1000        0x09        /* 1000BASE-T control          */
#define MII_STAT1000        0x0a        /* 1000BASE-T status           */
#define MII_ESTATUS         0x0f        /* Extended Status */
#define MII_DCOUNTER        0x12        /* Disconnect counter          */
#define MII_FCSCOUNTER      0x13        /* False carrier counter       */
#define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
#define MII_RERRCOUNTER     0x15        /* Receive error counter       */
#define MII_SREVISION       0x16        /* Silicon revision            */
#define MII_RESV1           0x17        /* Reserved...                 */
#define MII_LBRERROR        0x18        /* Lpback, rx, bypass error    */
#define MII_PHYADDR         0x19        /* PHY address                 */
#define MII_RESV2           0x1a        /* Reserved...                 */
#define MII_TPISTATUS       0x1b        /* TPI status for 10mbps       */
#define MII_NCONFIG         0x1c        /* Network interface config    */

/* Basic mode control register. */
#define BMCR_RESV               0x003f  /* Unused...                   */
#define BMCR_SPEED1000          0x0040  /* MSB of Speed (1000)         */
#define BMCR_CTST               0x0080  /* Collision test              */
#define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
#define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
#define BMCR_ISOLATE            0x0400  /* Disconnect DP83840 from MII */
#define BMCR_PDOWN              0x0800  /* Powerdown the DP83840       */
#define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
#define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
#define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
#define BMCR_RESET              0x8000  /* Reset the DP83840           */

/* Basic mode status register. */
#define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
#define BMSR_JCD                0x0002  /* Jabber detected             */
#define BMSR_LSTATUS            0x0004  /* Link status                 */
#define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
#define BMSR_RFAULT             0x0010  /* Remote fault detected       */
#define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
#define BMSR_RESV               0x00c0  /* Unused...                   */
#define BMSR_ESTATEN            0x0100  /* Extended Status in R15 */
#define BMSR_100FULL2           0x0200  /* Can do 100BASE-T2 HDX */
#define BMSR_100HALF2           0x0400  /* Can do 100BASE-T2 FDX */
#define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
#define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
#define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
#define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
#define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets  */

/* Advertisement control register. */
#define ADVERTISE_SLCT          0x001f  /* Selector bits               */
#define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
#define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
#define ADVERTISE_1000XFULL     0x0020  /* Try for 1000BASE-X full-duplex */
#define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
#define ADVERTISE_1000XHALF     0x0040  /* Try for 1000BASE-X half-duplex */
#define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
#define ADVERTISE_1000XPAUSE    0x0080  /* Try for 1000BASE-X pause    */
#define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
#define ADVERTISE_1000XPSE_ASYM 0x0100  /* Try for 1000BASE-X asym pause */
#define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
#define ADVERTISE_PAUSE_CAP     0x0400  /* Try for pause               */
#define ADVERTISE_PAUSE_ASYM    0x0800  /* Try for asymetric pause     */
#define ADVERTISE_RESV          0x1000  /* Unused...                   */
#define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
#define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */
#define ADVERTISE_NPAGE         0x8000  /* Next page bit               */

#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
            ADVERTISE_CSMA)
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
                       ADVERTISE_100HALF | ADVERTISE_100FULL)

/* Link partner ability register. */
#define LPA_SLCT                0x001f  /* Same as advertise selector  */
#define LPA_10HALF              0x0020  /* Can do 10mbps half-duplex   */
#define LPA_1000XFULL           0x0020  /* Can do 1000BASE-X full-duplex */
#define LPA_10FULL              0x0040  /* Can do 10mbps full-duplex   */
#define LPA_1000XHALF           0x0040  /* Can do 1000BASE-X half-duplex */
#define LPA_100HALF             0x0080  /* Can do 100mbps half-duplex  */
#define LPA_1000XPAUSE          0x0080  /* Can do 1000BASE-X pause     */
#define LPA_100FULL             0x0100  /* Can do 100mbps full-duplex  */
#define LPA_1000XPAUSE_ASYM     0x0100  /* Can do 1000BASE-X pause asym*/
#define LPA_100BASE4            0x0200  /* Can do 100mbps 4k packets   */
#define LPA_PAUSE_CAP           0x0400  /* Can pause                   */
#define LPA_PAUSE_ASYM          0x0800  /* Can pause asymetrically     */
#define LPA_RESV                0x1000  /* Unused...                   */
#define LPA_RFAULT              0x2000  /* Link partner faulted        */
#define LPA_LPACK               0x4000  /* Link partner acked us       */
#define LPA_NPAGE               0x8000  /* Next page bit               */

#define LPA_DUPLEX      (LPA_10FULL | LPA_100FULL)
#define LPA_100         (LPA_100FULL | LPA_100HALF | LPA_100BASE4)

/* Expansion register for auto-negotiation. */
#define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
#define EXPANSION_LCWP          0x0002  /* Got new RX page code word   */
#define EXPANSION_ENABLENPAGE   0x0004  /* This enables npage words    */
#define EXPANSION_NPCAPABLE     0x0008  /* Link partner supports npage */
#define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
#define EXPANSION_RESV          0xffe0  /* Unused...                   */

#define ESTATUS_1000_TFULL  0x2000  /* Can do 1000BT Full */
#define ESTATUS_1000_THALF  0x1000  /* Can do 1000BT Half */

/* N-way test register. */
#define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
#define NWAYTEST_LOOPBACK       0x0100  /* Enable loopback for N-way   */
#define NWAYTEST_RESV2          0xfe00  /* Unused...                   */

/* 1000BASE-T Control register */
#define ADVERTISE_1000FULL      0x0200  /* Advertise 1000BASE-T full duplex */
#define ADVERTISE_1000HALF      0x0100  /* Advertise 1000BASE-T half duplex */

/* 1000BASE-T Status register */
#define LPA_1000LOCALRXOK       0x2000  /* Link partner local receiver status */
#define LPA_1000REMRXOK         0x1000  /* Link partner remote receiver status */
#define LPA_1000FULL            0x0800  /* Link partner 1000BASE-T full duplex */
#define LPA_1000HALF            0x0400  /* Link partner 1000BASE-T half duplex */

/* 芯片参数和芯片寄存器定义 */

#define SMC911X_TX_FIFO_LOW_THRESHOLD   (1536*2) /* TX FIFO 门槛值 */

/* 定义的值为BASE ADDR的偏移量 */
#define RX_DATA_FIFO         (0x00) /* RX data FIFO port */

#define TX_DATA_FIFO         (0x20 >> SMC9218_BUS_OFF ) /* TX data FIFO port */
#define TX_CMD_A_INT_ON_COMP_       (0x80000000) /* interrupt on complition */
#define TX_CMD_A_INT_BUF_END_ALGN_  (0x03000000) /* buffer end alignment */
#define TX_CMD_A_INT_4_BYTE_ALGN_   (0x00000000) /* 4 bytes alignment */
#define TX_CMD_A_INT_16_BYTE_ALGN_  (0x01000000) /* 16 bytes alignment */
#define TX_CMD_A_INT_32_BYTE_ALGN_  (0x02000000) /* 32 bytes alignment */
#define TX_CMD_A_INT_DATA_OFFSET_   (0x001F0000) /* data start offset */
#define TX_CMD_A_INT_FIRST_SEG_     (0x00002000) /* first segment */
#define TX_CMD_A_INT_LAST_SEG_      (0x00001000) /* last segment */
#define TX_CMD_A_BUF_SIZE_          (0x000007FF) /* buffer size */
#define TX_CMD_B_PKT_TAG_           (0xFFFF0000) /* packet tag */
#define TX_CMD_B_ADD_CRC_DISABLE_   (0x00002000) /* add crc disable*/
#define TX_CMD_B_DISABLE_PADDING_   (0x00001000) /* disable ethernet frame padding */
#define TX_CMD_B_PKT_BYTE_LENGTH_   (0x000007FF) /* packet length */

#define RX_STATUS_FIFO          (0x40 >> SMC9218_BUS_OFF) /* rx status fifo port */
#define RX_STS_PKT_LEN_         (0x3FFF0000) /* packet len */
#define RX_STS_ES_              (0x00008000) /* Error status */
#define RX_STS_BCST_            (0x00002000) /* broadcast frame */
#define RX_STS_LEN_ERR_         (0x00001000) /* length error */
#define RX_STS_RUNT_ERR_        (0x00000800) /* runt frame */
#define RX_STS_MCAST_           (0x00000400) /* multicast frame */
#define RX_STS_TOO_LONG_        (0x00000080) /* frame too long */
#define RX_STS_COLL_            (0x00000040) /* collision seen */
#define RX_STS_ETH_TYPE_        (0x00000020) /* frame type */
#define RX_STS_WDOG_TMT_        (0x00000010) /* receive watchdog time-out */
#define RX_STS_MII_ERR_         (0x00000008) /* mii error */
#define RX_STS_DRIBBLING_       (0x00000004) /* dribbling bit */
#define RX_STS_CRC_ERR_         (0x00000002) /* crc error */

#define RX_STATUS_FIFO_PEEK     (0x44 >> SMC9218_BUS_OFF ) /* rx status fifo peek */

#define TX_STATUS_FIFO          (0x48 >> SMC9218_BUS_OFF ) /* tx status fifo port */
#define TX_STS_TAG_             (0xFFFF0000) /* packet tag */
#define TX_STS_ES_              (0x00008000) /* error status */
#define TX_STS_LOC_             (0x00000800) /* lose of carrier */
#define TX_STS_NO_CARR_         (0x00000400) /* no carrier */
#define TX_STS_LATE_COLL_       (0x00000200) /* late collision */
#define TX_STS_MANY_COLL_       (0x00000100) /* excessive collision */
#define TX_STS_COLL_CNT_        (0x00000078) /* collision count */
#define TX_STS_MANY_DEFER_      (0x00000004) /* excessive deferral */
#define TX_STS_UNDERRUN_        (0x00000002) /* underrun error */
#define TX_STS_DEFERRED_        (0x00000001) /* deferred */

#define TX_STATUS_FIFO_PEEK     (0x4C >> SMC9218_BUS_OFF) /* tx status fifo peek */

#define ID_REV                  (0x50 >> SMC9218_BUS_OFF) /* chip id and revision */
#define ID_REV_CHIP_ID_         (0xFFFF0000)  /* RO chip id */
#define ID_REV_REV_ID_          (0x0000FFFF)  /* RO revision */

#define INT_CFG                 (0x54 >> SMC9218_BUS_OFF) /* main interrupt configuration */
#define INT_CFG_INT_DEAS_       (0xFF000000) /* interrupt deassertion interval */
#define INT_CFG_INT_DEAS_CLR_   (0x00004000) /* interrupt deassertion interval clear */
#define INT_CFG_INT_DEAS_STS_   (0x00002000) /* status */
#define INT_CFG_IRQ_INT_        (0x00001000)  /* master interrupt */
#define INT_CFG_IRQ_EN_         (0x00000100)  /* IRQ enable */
#define INT_CFG_IRQ_POL_        (0x00000010)  /* IRQ polarity */
#define INT_CFG_IRQ_TYPE_       (0x00000001)  /* IRQ buffer type */

#define INT_STS                 (0x58 >> SMC9218_BUS_OFF) /* interrupt status register */
#define INT_STS_SW_INT_         (0x80000000)  /* software interrupt */
#define INT_STS_TXSTOP_INT_     (0x02000000)  /* tx stopped  */
#define INT_STS_RXSTOP_INT_     (0x01000000)  /* rx stopped */
#define INT_STS_RXDFH_INT_      (0x00800000)  /* rx dropped frame counter halfway */
#define INT_STS_TX_IOC_         (0x00200000)  /* Tx IOC interrupt */
#define INT_STS_RXD_INT_        (0x00100000)  /* rx dma interrupt */
#define INT_STS_GPT_INT_        (0x00080000)  /* gp timer */
#define INT_STS_PHY_INT_        (0x00040000)  /* PHY interrupt */
#define INT_STS_PME_INT_        (0x00020000)  /* power managment event interrupt */
#define INT_STS_TXSO_           (0x00010000)  /* tx status fifo overflow */
#define INT_STS_RWT_            (0x00008000)  /* receive watchdog time-out */
#define INT_STS_RXE_            (0x00004000)  /* receive error */
#define INT_STS_TXE_            (0x00002000)  /* transmitter error */
#define INT_STS_TDFU_           (0x00000800)  /* tx data fifo underrun interrupt */
#define INT_STS_TDFO_           (0x00000400)  /* tx data fifo overrun interrupt  */
#define INT_STS_TDFA_           (0x00000200)  /* tx data fifo available interrupt */
#define INT_STS_TSFF_           (0x00000100)  /* tx status fifo full interrupt */
#define INT_STS_TSFL_           (0x00000080)  /* tx status fifo level interrupt */
#define INT_STS_RXDF_           (0x00000040)  /* rx dropped frame interrupt */
#define INT_STS_RDFL_           (0x00000020)  /* rx data fifo level interrupt */
#define INT_STS_RSFF_           (0x00000010)  /* rx status fifo full interrupt */
#define INT_STS_RSFL_           (0x00000008)  /* rx status fifo level interrupt */
#define INT_STS_GPIO2_INT_      (0x00000004)  /* R/WC */
#define INT_STS_GPIO1_INT_      (0x00000002)  /* R/WC */
#define INT_STS_GPIO0_INT_      (0x00000001)  /* R/WC */

#define INT_EN                  (0x5C >> SMC9218_BUS_OFF) /* interrupt enable register*/
#define INT_EN_SW_INT_EN_       (0x80000000)  /* software interrupt */
#define INT_EN_TXSTOP_INT_EN_   (0x02000000)  /* tx stopped interrupt enable */
#define INT_EN_RXSTOP_INT_EN_   (0x01000000)  /* rx stopped interrupt enable */
#define INT_EN_RXDFH_INT_EN_    (0x00800000)  /* rx dropped frame counter halfway interrupt enable */
#define INT_EN_TIOC_INT_EN_     (0x00200000)  /* Tx IOC interrupt enable */
#define INT_EN_RXD_INT_EN_      (0x00100000)  /* rx dama interrupt enable */
#define INT_EN_GPT_INT_EN_      (0x00080000)  /* GP timer */
#define INT_EN_PHY_INT_EN_      (0x00040000)  /* PHY */
#define INT_EN_PME_INT_EN_      (0x00020000)  /* Power managment event interrupt enable */
#define INT_EN_TXSO_EN_         (0x00010000)  /* tx status fifo overflow */
#define INT_EN_RWT_EN_          (0x00008000)  /* receive watchdog time-out */
#define INT_EN_RXE_EN_          (0x00004000)  /* receiver error */
#define INT_EN_TXE_EN_          (0x00002000)  /* transmitter error */
#define INT_EN_TDFU_EN_         (0x00000800)  /* tx data fifo underrun  */
#define INT_EN_TDFO_EN_         (0x00000400)  /* tx data fifo overrun */
#define INT_EN_TDFA_EN_         (0x00000200)  /* tx data fifo available */
#define INT_EN_TSFF_EN_         (0x00000100)  /* tx status fifo full */
#define INT_EN_TSFL_EN_         (0x00000080)  /* tx status fifo level */
#define INT_EN_RXDF_EN_         (0x00000040)  /* rx dropped frame */
#define INT_EN_RDFL_EN_         (0x00000020)  /* rx data fifo level */
#define INT_EN_RSFF_EN_         (0x00000010)  /* rx status fifo full */
#define INT_EN_RSFL_EN_         (0x00000008)  /* rx status fifo level */