de2_lcm_test.tan.summary

基于Quartus的TFT－LCD测试程序

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.311 ns
From           : GPIO_0[34]
To             : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1]
From Clock     : --
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 14.927 ns
From           : I2S_LCM_Config:u4|I2S_Controller:u0|mST[1]
To             : GPIO_0[34]
From Clock     : CLOCK_50
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 10.326 ns
From           : KEY[0]
To             : TD_RESET
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.341 ns
From           : altera_internal_jtag
To             : sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register|dffs[9]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'CLOCK_50'
Slack          : 4.489 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 90.73 MHz ( period = 11.022 ns )
From           : I2S_LCM_Config:u4|I2S_Controller:u0|mST[4]
To             : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10]
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Clock Setup: 'LCM_PLL:u0|altpll:altpll_component|_clk0'
Slack          : 49.396 ns
Required Time  : 18.42 MHz ( period = 54.285 ns )
Actual Time    : 204.54 MHz ( period = 4.889 ns )
From           : H_Cont[10]
To             : Tmp_DATA[7]
From Clock     : LCM_PLL:u0|altpll:altpll_component|_clk0
To Clock       : LCM_PLL:u0|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 97.33 MHz ( period = 10.274 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4]
To             : sld_hub:sld_hub_inst|hub_tdo_reg
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'LCM_PLL:u0|altpll:altpll_component|_clk0'
Slack          : 0.391 ns
Required Time  : 18.42 MHz ( period = 54.285 ns )
Actual Time    : N/A
From           : oVGA_V_SYNC
To             : oVGA_V_SYNC
From Clock     : LCM_PLL:u0|altpll:altpll_component|_clk0
To Clock       : LCM_PLL:u0|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'CLOCK_50'
Slack          : 0.391 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : I2S_LCM_Config:u4|LUT_INDEX[0]
To             : I2S_LCM_Config:u4|LUT_INDEX[0]
From Clock     : CLOCK_50
To Clock       : CLOCK_50
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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