altsyncram_c4l1.tdf

基于Quartus的TFT－LCD测试程序

			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 13,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 5,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 13,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a45 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 13,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 6,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 13,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a46 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 13,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 7,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 13,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a47 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 13,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 8,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 13,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a48 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 9,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 13,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 9,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 13,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a49 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 13,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 10,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 13,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a50 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 13,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 11,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 13,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a51 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 12,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 12288,
			PORT_A_FIRST_BIT_NUMBER = 12,
			PORT_A_LAST_ADDRESS = 16383,
			PORT_A_LOGICAL_RAM_DEPTH = 16384,
			PORT_A_LOGICAL_RAM_WIDTH = 13,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 12,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 12288,
			PORT_B_FIRST_BIT_NUMBER = 12,
			PORT_B_LAST_ADDRESS = 16383,
			PORT_B_LOGICAL_RAM_DEPTH = 16384,
			PORT_B_LOGICAL_RAM_WIDTH = 13,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	address_a_sel[1..0]	: WIRE;
	address_a_wire[13..0]	: WIRE;
	address_b_sel[1..0]	: WIRE;
	address_b_wire[13..0]	: WIRE;

BEGIN 
	address_reg_a[].clk = clock0;
	address_reg_a[].d = address_a_sel[];
	address_reg_a[].ena = clocken0;
	address_reg_b[].clk = clock1;
	address_reg_b[].d = address_b_sel[];
	address_reg_b[].ena = clocken1;
	decode3.data[1..0] = address_a_wire[13..12];
	decode3.enable = wren_a;
	decode4.data[1..0] = address_b_wire[13..12];
	decode4.enable = wren_b;
	decode_a.data[1..0] = address_a_wire[13..12];
	decode_a.enable = clocken0;
	decode_b.data[1..0] = address_b_wire[13..12];
	decode_b.enable = clocken1;
	mux5.data[] = ( ram_block2a[51..0].portadataout[0..0]);
	mux5.sel[] = address_reg_a[].q;
	mux6.data[] = ( ram_block2a[51..0].portbdataout[0..0]);
	mux6.sel[] = address_reg_b[].q;
	ram_block2a[51..0].clk0 = clock0;
	ram_block2a[51..0].clk1 = clock1;
	ram_block2a[51..0].ena0 = ( decode_a.eq[3..3], decode_a.eq[3..3], decode_a.eq[3..3], decode_a.eq[3..3], decode_a.eq[3..3], decode_a.eq[3..3], decode_a.eq[3..3], decode_a.eq[3..3], decode_a.eq[3..3], decode_a.eq[3..3], decode_a.eq[3..3], decode_a.eq[3..3], decode_a.eq[3..2], decode_a.eq[2..2], decode_a.eq[2..2], decode_a.eq[2..2], decode_a.eq[2..2], decode_a.eq[2..2], decode_a.eq[2..2], decode_a.eq[2..2], decode_a.eq[2..2], decode_a.eq[2..2], decode_a.eq[2..2], decode_a.eq[2..2], decode_a.eq[2..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0]);
	ram_block2a[51..0].ena1 = ( decode_b.eq[3..3], decode_b.eq[3..3], decode_b.eq[3..3], decode_b.eq[3..3], decode_b.eq[3..3], decode_b.eq[3..3], decode_b.eq[3..3], decode_b.eq[3..3], decode_b.eq[3..3], decode_b.eq[3..3], decode_b.eq[3..3], decode_b.eq[3..3], decode_b.eq[3..2], decode_b.eq[2..2], decode_b.eq[2..2], decode_b.eq[2..2], decode_b.eq[2..2], decode_b.eq[2..2], decode_b.eq[2..2], decode_b.eq[2..2], decode_b.eq[2..2], decode_b.eq[2..2], decode_b.eq[2..2], decode_b.eq[2..2], decode_b.eq[2..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0]);
	ram_block2a[51..0].portaaddr[] = ( address_a_wire[11..0]);
	ram_block2a[0].portadatain[] = ( data_a[0..0]);
	ram_block2a[1].portadatain[] = ( data_a[1..1]);
	ram_block2a[2].portadatain[] = ( data_a[2..2]);
	ram_block2a[3].portadatain[] = ( data_a[3..3]);
	ram_block2a[4].portadatain[] = ( data_a[4..4]);
	ram_block2a[5].portadatain[] = ( data_a[5..5]);
	ram_block2a[6].portadatain[] = ( data_a[6..6]);
	ram_block2a[7].portadatain[] = ( data_a[7..7]);
	ram_block2a[8].portadatain[] = ( data_a[8..8]);
	ram_block2a[9].portadatain[] = ( data_a[9..9]);
	ram_block2a[10].portadatain[] = ( data_a[10..10]);
	ram_block2a[11].portadatain[] = ( data_a[11..11]);
	ram_block2a[12].portadatain[] = ( data_a[12..12]);
	ram_block2a[13].portadatain[] = ( data_a[0..0]);
	ram_block2a[14].portadatain[] = ( data_a[1..1]);
	ram_block2a[15].portadatain[] = ( data_a[2..2]);
	ram_block2a[16].portadatain[] = ( data_a[3..3]);
	ram_block2a[17].portadatain[] = ( data_a[4..4]);
	ram_block2a[18].portadatain[] = ( data_a[5..5]);
	ram_block2a[19].portadatain[] = ( data_a[6..6]);
	ram_block2a[20].portadatain[] = ( data_a[7..7]);
	ram_block2a[21].portadatain[] = ( data_a[8..8]);
	ram_block2a[22].portadatain[] = ( data_a[9..9]);
	ram_block2a[23].portadatain[] = ( data_a[10..10]);
	ram_block2a[24].portadatain[] = ( data_a[11..11]);
	ram_block2a[25].portadatain[] = ( data_a[12..12]);
	ram_block2a[26].portadatain[] = ( data_a[0..0]);
	ram_block2a[27].portadatain[] = ( data_a[1..1]);
	ram_block2a[28].portadatain[] = ( data_a[2..2]);
	ram_block2a[29].portadatain[] = ( data_a[3..3]);
	ram_block2a[30].portadatain[] = ( data_a[4..4]);
	ram_block2a[31].portadatain[] = ( data_a[5..5]);
	ram_block2a[32].portadatain[] = ( data_a[6..6]);
	ram_block2a[33].portadatain[] = ( data_a[7..7]);
	ram_block2a[34].portadatain[] = ( data_a[8..8]);
	ram_block2a[35].portadatain[] = ( data_a[9..9]);
	ram_block2a[36].portadatain[] = ( data_a[10..10]);
	ram_block2a[37].portadatain[] = ( data_a[11..11]);
	ram_block2a[38].portadatain[] = ( data_a[12..12]);
	ram_block2a[39].portadatain[] = ( data_a[0..0]);
	ram_block2a[40].portadatain[] = ( data_a[1..1]);
	ram_block2a[41].portadatain[] = ( data_a[2..2]);
	ram_block2a[42].portadatain[] = ( data_a[3..3]);
	ram_block2a[43].portadatain[] = ( data_a[4..4]);
	ram_block2a[44].portadatain[] = ( data_a[5..5]);
	ram_block2a[45].portadatain[] = ( data_a[6..6]);
	ram_block2a[46].portadatain[] = ( data_a[7..7]);
	ram_block2a[47].portadatain[] = ( data_a[8..8]);
	ram_block2a[48].portadatain[] = ( data_a[9..9]);
	ram_block2a[49].portadatain[] = ( data_a[10..10]);
	ram_block2a[50].portadatain[] = ( data_a[11..11]);
	ram_block2a[51].portadatain[] = ( data_a[12..12]);
	ram_block2a[51..0].portawe = ( decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..3], decode3.eq[3..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..2], decode3.eq[2..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]);
	ram_block2a[51..0].portbaddr[] = ( address_b_wire[11..0]);
	ram_block2a[0].portbdatain[] = ( data_b[0..0]);
	ram_block2a[1].portbdatain[] = ( data_b[1..1]);
	ram_block2a[2].portbdatain[] = ( data_b[2..2]);
	ram_block2a[3].portbdatain[] = ( data_b[3..3]);
	ram_block2a[4].portbdatain[] = ( data_b[4..4]);
	ram_block2a[5].portbdatain[] = ( data_b[5..5]);
	ram_block2a[6].portbdatain[] = ( data_b[6..6]);
	ram_block2a[7].portbdatain[] = ( data_b[7..7]);
	ram_block2a[8].portbdatain[] = ( data_b[8..8]);
	ram_block2a[9].portbdatain[] = ( data_b[9..9]);
	ram_block2a[10].portbdatain[] = ( data_b[10..10]);
	ram_block2a[11].portbdatain[] = ( data_b[11..11]);
	ram_block2a[12].portbdatain[] = ( data_b[12..12]);
	ram_block2a[13].portbdatain[] = ( data_b[0..0]);
	ram_block2a[14].portbdatain[] = ( data_b[1..1]);
	ram_block2a[15].portbdatain[] = ( data_b[2..2]);
	ram_block2a[16].portbdatain[] = ( data_b[3..3]);
	ram_block2a[17].portbdatain[] = ( data_b[4..4]);
	ram_block2a[18].portbdatain[] = ( data_b[5..5]);
	ram_block2a[19].portbdatain[] = ( data_b[6..6]);
	ram_block2a[20].portbdatain[] = ( data_b[7..7]);
	ram_block2a[21].portbdatain[] = ( data_b[8..8]);
	ram_block2a[22].portbdatain[] = ( data_b[9..9]);