de2_lcm_test.hif

基于Quartus的TFT－LCD测试程序

PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKBAD0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKBAD1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK4
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK5
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK6
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK7
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK8
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK9
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANDATA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANDATAOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANDONE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ACTIVECLOCK
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKLOSS
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_INCLK1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_INCLK0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_FBIN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PLLENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKSWITCH
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ARESET
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PFDENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANCLK
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANACLR
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANREAD
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANWRITE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_LOCKED
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CONFIGUPDATE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_FBOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEDONE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASESTEP
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEUPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANCLKENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASECOUNTERSELECT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
NOTHING
PARAMETER_UNKNOWN
DEF
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
6
PARAMETER_UNKNOWN
DEF
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk
-1
3
clk
-1
3
}
# include_file {
..|..|altera|71|quartus|libraries|megafunctions|stratixii_pll.inc
6d1985e16ab5f59a1fd6b0ae20978a4e
..|..|altera|71|quartus|libraries|megafunctions|aglobal71.inc
80b63f71158cd1a01acf29ef94ccd6
..|..|altera|71|quartus|libraries|megafunctions|stratix_pll.inc
5f8211898149ceae8264a0ea5036254f
..|..|altera|71|quartus|libraries|megafunctions|cycloneii_pll.inc
39a0d9d1237d1db39c848c3f9faffc
}
# lmf
..|..|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
I2S_LCM_Config
# storage
db|DE2_LCM_Test.(3).cnf
db|DE2_LCM_Test.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
I2S_LCM_Config.v
d9e7ae7cdc6b651855c13ebf281e921c
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
LUT_SIZE
8
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
I2S_LCM_Config:u4
}
# lmf
..|..|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
I2S_Controller
# storage
db|DE2_LCM_Test.(4).cnf
db|DE2_LCM_Test.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
I2S_Controller.v
f0395ff46ba8a0901d572b148d4c69bc
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
CLK_Freq
50000000
PARAMETER_SIGNED_DEC
DEF
I2S_Freq
20000
PARAMETER_SIGNED_DEC
DEF
}
# hierarchies {
I2S_LCM_Config:u4|I2S_Controller:u0
}
# lmf
..|..|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
LCM_PLL
# storage
db|DE2_LCM_Test.(1).cnf
db|DE2_LCM_Test.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
LCM_PLL.v
5b51ab2d18a216109bfedc7bd863fd93
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
LCM_PLL:u0
}
# lmf
..|..|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
altpll
# storage
db|DE2_LCM_Test.(5).cnf
db|DE2_LCM_Test.(5).cnf
# case_insensitive
# source_file
..|..|altera|71|quartus|libraries|megafunctions|altpll.tdf
eb3be4988f6354a2ecd98179c125dde
6
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
20000
PARAMETER_SIGNED_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_GATED_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
SELF_RESET_ON_LOSS_LOCK
OFF
PARAMETER_UNKNOWN
DEF
CLK9_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_MULTIPLY_BY
921
PARAMETER_SIGNED_DEC
USR
CLK9_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK8_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK7_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK6_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
CLK5_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK4_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
CLK0_DIVIDE_BY
2500
PARAMETER_SIGNED_DEC
USR
CLK9_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK8_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK7_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK6_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK5_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK4_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
CLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
USR
CLK5_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK4_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
CLK9_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK8_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK7_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK6_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK5_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK4_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
CLK0_DUTY_CYCLE
50
PARAMETER_SIGNED_DEC
USR
CLK9_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_MODE
OFF
PARAMETER_UNKNOWN
DEF
CLK9_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK8_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK7_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK6_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK5_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK4_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK3_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK2_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK1_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
CLK0_USE_EVEN_COUNTER_VALUE
OFF
PARAMETER_UNKNOWN
DEF
LOCK_WINDOW_UI
 0.05
PARAMETER_UNKNOWN
DEF
EXTCLK3_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_MULTIPLY_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK2_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK1_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK0_DIVIDE_BY
1
PARAMETER_UNKNOWN
DEF
EXTCLK3_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK2_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK1_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
EXTCLK0_DUTY_CYCLE
50
PARAMETER_UNKNOWN
DEF
VCO_MULTIPLY_BY
0
PARAMETER_UNKNOWN
DEF
VCO_DIVIDE_BY
0
PARAMETER_UNKNOWN
DEF
SCLKOUT0_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
SCLKOUT1_PHASE_SHIFT
0
PARAMETER_UNKNOWN
DEF
VCO_MIN
0
PARAMETER_UNKNOWN
DEF
VCO_MAX
0
PARAMETER_UNKNOWN
DEF
VCO_CENTER
0
PARAMETER_UNKNOWN
DEF
PFD_MIN
0
PARAMETER_UNKNOWN
DEF
PFD_MAX
0
PARAMETER_UNKNOWN
DEF
M_INITIAL
0
PARAMETER_UNKNOWN
DEF
M
0
PARAMETER_UNKNOWN
DEF
N
1
PARAMETER_UNKNOWN
DEF
M2
1
PARAMETER_UNKNOWN
DEF
N2
1
PARAMETER_UNKNOWN
DEF
SS
1
PARAMETER_UNKNOWN
DEF
C0_HIGH
0
PARAMETER_UNKNOWN
DEF
C1_HIGH
0
PARAMETER_UNKNOWN
DEF
C2_HIGH
0
PARAMETER_UNKNOWN
DEF
C3_HIGH
0
PARAMETER_UNKNOWN
DEF
C4_HIGH
0
PARAMETER_UNKNOWN
DEF
C5_HIGH
0
PARAMETER_UNKNOWN
DEF
C6_HIGH
0
PARAMETER_UNKNOWN
DEF
C7_HIGH
0
PARAMETER_UNKNOWN
DEF
C8_HIGH
0
PARAMETER_UNKNOWN
DEF
C9_HIGH
0
PARAMETER_UNKNOWN
DEF
C0_LOW
0
PARAMETER_UNKNOWN
DEF
C1_LOW
0
PARAMETER_UNKNOWN
DEF
C2_LOW
0
PARAMETER_UNKNOWN
DEF
C3_LOW
0
PARAMETER_UNKNOWN
DEF
C4_LOW
0
PARAMETER_UNKNOWN
DEF
C5_LOW
0
PARAMETER_UNKNOWN
DEF
C6_LOW
0
PARAMETER_UNKNOWN
DEF
C7_LOW
0
PARAMETER_UNKNOWN
DEF
C8_LOW
0
PARAMETER_UNKNOWN
DEF
C9_LOW
0
PARAMETER_UNKNOWN
DEF
C0_INITIAL
0
PARAMETER_UNKNOWN
DEF
C1_INITIAL
0
PARAMETER_UNKNOWN
DEF
C2_INITIAL
0
PARAMETER_UNKNOWN
DEF
C3_INITIAL
0
PARAMETER_UNKNOWN
DEF
C4_INITIAL
0
PARAMETER_UNKNOWN
DEF
C5_INITIAL
0
PARAMETER_UNKNOWN
DEF
C6_INITIAL
0
PARAMETER_UNKNOWN
DEF
C7_INITIAL
0
PARAMETER_UNKNOWN
DEF
C8_INITIAL
0
PARAMETER_UNKNOWN
DEF
C9_INITIAL
0
PARAMETER_UNKNOWN
DEF
C0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C4_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C5_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C6_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C7_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C8_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C9_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
C0_PH
0
PARAMETER_UNKNOWN
DEF
C1_PH
0
PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
C6_PH
0
PARAMETER_UNKNOWN
DEF
C7_PH
0
PARAMETER_UNKNOWN
DEF
C8_PH
0
PARAMETER_UNKNOWN