prev_cmp_de2_lcm_test.tan.qmsg

基于Quartus的TFT－LCD测试程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\] register sld_hub:sld_hub_inst\|hub_tdo_reg 97.33 MHz 10.274 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 97.33 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo_reg\" (period= 10.274 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.916 ns + Longest register register " "Info: + Longest register to register delay is 4.916 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\] 1 REG LCFF_X30_Y13_N27 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X30_Y13_N27; Fanout = 16; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } } { "../../altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "D:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.223 ns) + CELL(0.271 ns) 1.494 ns sld_hub:sld_hub_inst\|hub_tdo_reg~759 2 COMB LCCOMB_X31_Y20_N2 1 " "Info: 2: + IC(1.223 ns) + CELL(0.271 ns) = 1.494 ns; Loc. = LCCOMB_X31_Y20_N2; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~759'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.494 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo_reg~759 } "NODE_NAME" } } { "../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.060 ns) + CELL(0.438 ns) 2.992 ns sld_hub:sld_hub_inst\|hub_tdo_reg~760 3 COMB LCCOMB_X31_Y15_N26 1 " "Info: 3: + IC(1.060 ns) + CELL(0.438 ns) = 2.992 ns; Loc. = LCCOMB_X31_Y15_N26; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~760'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.498 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~759 sld_hub:sld_hub_inst|hub_tdo_reg~760 } "NODE_NAME" } } { "../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.254 ns) + CELL(0.419 ns) 3.665 ns sld_hub:sld_hub_inst\|hub_tdo_reg~762 4 COMB LCCOMB_X31_Y15_N10 1 " "Info: 4: + IC(0.254 ns) + CELL(0.419 ns) = 3.665 ns; Loc. = LCCOMB_X31_Y15_N10; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~762'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.673 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~760 sld_hub:sld_hub_inst|hub_tdo_reg~762 } "NODE_NAME" } } { "../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.752 ns) + CELL(0.415 ns) 4.832 ns sld_hub:sld_hub_inst\|hub_tdo_reg~763 5 COMB LCCOMB_X30_Y12_N22 1 " "Info: 5: + IC(0.752 ns) + CELL(0.415 ns) = 4.832 ns; Loc. = LCCOMB_X30_Y12_N22; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~763'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.167 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~762 sld_hub:sld_hub_inst|hub_tdo_reg~763 } "NODE_NAME" } } { "../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 4.916 ns sld_hub:sld_hub_inst\|hub_tdo_reg 6 REG LCFF_X30_Y12_N23 2 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 4.916 ns; Loc. = LCFF_X30_Y12_N23; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~763 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.627 ns ( 33.10 % ) " "Info: Total cell delay = 1.627 ns ( 33.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.289 ns ( 66.90 % ) " "Info: Total interconnect delay = 3.289 ns ( 66.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.916 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo_reg~759 sld_hub:sld_hub_inst|hub_tdo_reg~760 sld_hub:sld_hub_inst|hub_tdo_reg~762 sld_hub:sld_hub_inst|hub_tdo_reg~763 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.916 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo_reg~759 sld_hub:sld_hub_inst|hub_tdo_reg~760 sld_hub:sld_hub_inst|hub_tdo_reg~762 sld_hub:sld_hub_inst|hub_tdo_reg~763 sld_hub:sld_hub_inst|hub_tdo_reg } { 0.000ns 1.223ns 1.060ns 0.254ns 0.752ns 0.000ns } { 0.000ns 0.271ns 0.438ns 0.419ns 0.415ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.007 ns - Smallest " "Info: - Smallest clock skew is -0.007 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.448 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 4.448 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.888 ns) + CELL(0.000 ns) 2.888 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G1 1459 " "Info: 2: + IC(2.888 ns) + CELL(0.000 ns) = 2.888 ns; Loc. = CLKCTRL_G1; Fanout = 1459; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.888 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.537 ns) 4.448 ns sld_hub:sld_hub_inst\|hub_tdo_reg 3 REG LCFF_X30_Y12_N23 2 " "Info: 3: + IC(1.023 ns) + CELL(0.537 ns) = 4.448 ns; Loc. = LCFF_X30_Y12_N23; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.560 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 12.07 % ) " "Info: Total cell delay = 0.537 ns ( 12.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.911 ns ( 87.93 % ) " "Info: Total interconnect delay = 3.911 ns ( 87.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.448 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.448 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } { 0.000ns 2.888ns 1.023ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 4.455 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 4.455 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y19_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y19_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.888 ns) + CELL(0.000 ns) 2.888 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G1 1459 " "Info: 2: + IC(2.888 ns) + CELL(0.000 ns) = 2.888 ns; Loc. = CLKCTRL_G1; Fanout = 1459; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.888 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.537 ns) 4.455 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\] 3 REG LCFF_X30_Y13_N27 16 " "Info: 3: + IC(1.030 ns) + CELL(0.537 ns) = 4.455 ns; Loc. = LCFF_X30_Y13_N27; Fanout = 16; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.567 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } } { "../../altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "D:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 12.05 % ) " "Info: Total cell delay = 0.537 ns ( 12.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.918 ns ( 87.95 % ) " "Info: Total interconnect delay = 3.918 ns ( 87.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.455 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.455 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } { 0.000ns 2.888ns 1.030ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.448 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.448 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } { 0.000ns 2.888ns 1.023ns } { 0.000ns 0.000ns 0.537ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.455 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.455 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } { 0.000ns 2.888ns 1.030ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "../../altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "D:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "../../altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "D:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.916 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo_reg~759 sld_hub:sld_hub_inst|hub_tdo_reg~760 sld_hub:sld_hub_inst|hub_tdo_reg~762 sld_hub:sld_hub_inst|hub_tdo_reg~763 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.916 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] sld_hub:sld_hub_inst|hub_tdo_reg~759 sld_hub:sld_hub_inst|hub_tdo_reg~760 sld_hub:sld_hub_inst|hub_tdo_reg~762 sld_hub:sld_hub_inst|hub_tdo_reg~763 sld_hub:sld_hub_inst|hub_tdo_reg } { 0.000ns 1.223ns 1.060ns 0.254ns 0.752ns 0.000ns } { 0.000ns 0.271ns 0.438ns 0.419ns 0.415ns 0.084ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.448 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.448 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } { 0.000ns 2.888ns 1.023ns } { 0.000ns 0.000ns 0.537ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.455 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.455 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } { 0.000ns 2.888ns 1.030ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "LCM_PLL:u0\|altpll:altpll_component\|_clk0 register oVGA_V_SYNC register oVGA_V_SYNC 391 ps " "Info: Minimum slack time is 391 ps for clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" between source register \"oVGA_V_SYNC\" and destination register \"oVGA_V_SYNC\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.407 ns + Shortest register register " "Info: + Shortest register to register delay is 0.407 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns oVGA_V_SYNC 1 REG LCFF_X37_Y26_N23 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X37_Y26_N23; Fanout = 2; REG Node = 'oVGA_V_SYNC'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { oVGA_V_SYNC } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "D:/EDA/DE2_LCM_Test/DE2_LCM_Test.v" 470 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.323 ns) 0.323 ns oVGA_V_SYNC~483 2 COMB LCCOMB_X37_Y26_N22 1 " "Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X37_Y26_N22; Fanout = 1; COMB Node = 'oVGA_V_SYNC~483'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.323 ns" { oVGA_V_SYNC oVGA_V_SYNC~483 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "D:/EDA/DE2_LCM_Test/DE2_LCM_Test.v" 470 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.407 ns oVGA_V_SYNC 3 REG LCFF_X37_Y26_N23 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X37_Y26_N23; Fanout = 2; REG Node = 'oVGA_V_SYNC'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { oVGA_V_SYNC~483 oVGA_V_SYNC } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "D:/EDA/DE2_LCM_Test/DE2_LCM_Test.v" 470 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.407 ns ( 100.00 % ) " "Info: Total cell delay = 0.407 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.407 ns" { oVGA_V_SYNC oVGA_V_SYNC~483 oVGA_V_SYNC } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.407 ns" { oVGA_V_SYNC oVGA_V_SYNC~483 oVGA_V_SYNC } { 0.000ns 0.000ns 0.000ns } { 0.000ns 0.323ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.016 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.016 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -2.358 ns " "Info: + Latch edge is -2.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination LCM_PLL:u0\|altpll:altpll_component\|_clk0 54.285 ns -2.358 ns  50 " "Info: Clock period of Destination clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" is 54.285 ns with  offset of -2.358 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.358 ns " "Info: - Launch edge is -2.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source LCM_PLL:u0\|altpll:altpll_component\|_clk0 54.285 ns -2.358 ns  50 " "Info: Clock period of Source clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" is 54.285 ns with  offset of -2.358 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LCM_PLL:u0\|altpll:altpll_component\|_clk0 destination 2.618 ns + Longest register " "Info: + Longest clock path from clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" to destination register is 2.618 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCM_PLL:u0\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'LCM_PLL:u0\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCM_PLL:u0|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns LCM_PLL:u0\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 35 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 35; COMB Node = 'LCM_PLL:u0\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.537 ns) 2.618 ns oVGA_V_SYNC 3 REG LCFF_X37_Y26_N23 2 " "Info: 3: + IC(0.990 ns) + CELL(0.537 ns) = 2.618 ns; Loc. = LCFF_X37_Y26_N23; Fanout = 2; REG Node = 'oVGA_V_SYNC'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.527 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl oVGA_V_SYNC } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "D:/EDA/DE2_LCM_Test/DE2_LCM_Test.v" 470 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.51 % ) " "Info: Total cell delay = 0.537 ns ( 20.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.081 ns ( 79.49 % ) " "Info: Total interconnect delay = 2.081 ns ( 79.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.618 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl oVGA_V_SYNC } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.618 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl oVGA_V_SYNC } { 0.000ns 1.091ns 0.990ns } { 0.000ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LCM_PLL:u0\|altpll:altpll_component\|_clk0 source 2.618 ns - Shortest register " "Info: - Shortest clock path from clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" to source register is 2.618 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCM_PLL:u0\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'LCM_PLL:u0\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCM_PLL:u0|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns LCM_PLL:u0\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 35 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 35; COMB Node = 'LCM_PLL:u0\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/qu