📄 prev_cmp_de2_lcm_test.tan.qmsg
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{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" { } { } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "LCM_PLL:u0\|altpll:altpll_component\|_clk0 register H_Cont\[10\] register Tmp_DATA\[7\] 49.396 ns " "Info: Slack time is 49.396 ns for clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" between source register \"H_Cont\[10\]\" and destination register \"Tmp_DATA\[7\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "204.54 MHz 4.889 ns " "Info: Fmax is 204.54 MHz (period= 4.889 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "54.111 ns + Largest register register " "Info: + Largest register to register requirement is 54.111 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "54.285 ns + " "Info: + Setup relationship between source and destination is 54.285 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 51.927 ns " "Info: + Latch edge is 51.927 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination LCM_PLL:u0\|altpll:altpll_component\|_clk0 54.285 ns -2.358 ns 50 " "Info: Clock period of Destination clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" is 54.285 ns with offset of -2.358 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.358 ns " "Info: - Launch edge is -2.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source LCM_PLL:u0\|altpll:altpll_component\|_clk0 54.285 ns -2.358 ns 50 " "Info: Clock period of Source clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" is 54.285 ns with offset of -2.358 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.040 ns + Largest " "Info: + Largest clock skew is 0.040 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LCM_PLL:u0\|altpll:altpll_component\|_clk0 destination 2.654 ns + Shortest register " "Info: + Shortest clock path from clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" to destination register is 2.654 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCM_PLL:u0\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'LCM_PLL:u0\|altpll:altpll_component\|_clk0'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCM_PLL:u0|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns LCM_PLL:u0\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 35 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 35; COMB Node = 'LCM_PLL:u0\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.026 ns) + CELL(0.537 ns) 2.654 ns Tmp_DATA\[7\] 3 REG LCFF_X54_Y21_N17 2 " "Info: 3: + IC(1.026 ns) + CELL(0.537 ns) = 2.654 ns; Loc. = LCFF_X54_Y21_N17; Fanout = 2; REG Node = 'Tmp_DATA\[7\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.563 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl Tmp_DATA[7] } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "D:/EDA/DE2_LCM_Test/DE2_LCM_Test.v" 420 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.23 % ) " "Info: Total cell delay = 0.537 ns ( 20.23 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.117 ns ( 79.77 % ) " "Info: Total interconnect delay = 2.117 ns ( 79.77 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl Tmp_DATA[7] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl Tmp_DATA[7] } { 0.000ns 1.091ns 1.026ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LCM_PLL:u0\|altpll:altpll_component\|_clk0 source 2.614 ns - Longest register " "Info: - Longest clock path from clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" to source register is 2.614 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCM_PLL:u0\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'LCM_PLL:u0\|altpll:altpll_component\|_clk0'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { LCM_PLL:u0|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns LCM_PLL:u0\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 35 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 35; COMB Node = 'LCM_PLL:u0\|altpll:altpll_component\|_clk0~clkctrl'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.091 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/71/quartus/libraries/megafunctions/altpll.tdf" 880 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.986 ns) + CELL(0.537 ns) 2.614 ns H_Cont\[10\] 3 REG LCFF_X36_Y26_N31 6 " "Info: 3: + IC(0.986 ns) + CELL(0.537 ns) = 2.614 ns; Loc. = LCFF_X36_Y26_N31; Fanout = 6; REG Node = 'H_Cont\[10\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.523 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl H_Cont[10] } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "D:/EDA/DE2_LCM_Test/DE2_LCM_Test.v" 443 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.54 % ) " "Info: Total cell delay = 0.537 ns ( 20.54 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.077 ns ( 79.46 % ) " "Info: Total interconnect delay = 2.077 ns ( 79.46 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.614 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl H_Cont[10] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.614 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl H_Cont[10] } { 0.000ns 1.091ns 0.986ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl Tmp_DATA[7] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl Tmp_DATA[7] } { 0.000ns 1.091ns 1.026ns } { 0.000ns 0.000ns 0.537ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.614 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl H_Cont[10] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.614 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl H_Cont[10] } { 0.000ns 1.091ns 0.986ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "DE2_LCM_Test.v" "" { Text "D:/EDA/DE2_LCM_Test/DE2_LCM_Test.v" 443 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" { } { { "DE2_LCM_Test.v" "" { Text "D:/EDA/DE2_LCM_Test/DE2_LCM_Test.v" 420 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl Tmp_DATA[7] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl Tmp_DATA[7] } { 0.000ns 1.091ns 1.026ns } { 0.000ns 0.000ns 0.537ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.614 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl H_Cont[10] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.614 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl H_Cont[10] } { 0.000ns 1.091ns 0.986ns } { 0.000ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.715 ns - Longest register register " "Info: - Longest register to register delay is 4.715 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns H_Cont\[10\] 1 REG LCFF_X36_Y26_N31 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X36_Y26_N31; Fanout = 6; REG Node = 'H_Cont\[10\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { H_Cont[10] } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "D:/EDA/DE2_LCM_Test/DE2_LCM_Test.v" 443 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.515 ns) + CELL(0.438 ns) 0.953 ns always0~213 2 COMB LCCOMB_X37_Y26_N0 1 " "Info: 2: + IC(0.515 ns) + CELL(0.438 ns) = 0.953 ns; Loc. = LCCOMB_X37_Y26_N0; Fanout = 1; COMB Node = 'always0~213'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.953 ns" { H_Cont[10] always0~213 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(0.393 ns) 1.605 ns always0~215 3 COMB LCCOMB_X37_Y26_N6 1 " "Info: 3: + IC(0.259 ns) + CELL(0.393 ns) = 1.605 ns; Loc. = LCCOMB_X37_Y26_N6; Fanout = 1; COMB Node = 'always0~215'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.652 ns" { always0~213 always0~215 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.266 ns) + CELL(0.438 ns) 2.309 ns always0~214 4 COMB LCCOMB_X37_Y26_N16 10 " "Info: 4: + IC(0.266 ns) + CELL(0.438 ns) = 2.309 ns; Loc. = LCCOMB_X37_Y26_N16; Fanout = 10; COMB Node = 'always0~214'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.704 ns" { always0~215 always0~214 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.896 ns) + CELL(0.510 ns) 4.715 ns Tmp_DATA\[7\] 5 REG LCFF_X54_Y21_N17 2 " "Info: 5: + IC(1.896 ns) + CELL(0.510 ns) = 4.715 ns; Loc. = LCFF_X54_Y21_N17; Fanout = 2; REG Node = 'Tmp_DATA\[7\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.406 ns" { always0~214 Tmp_DATA[7] } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "D:/EDA/DE2_LCM_Test/DE2_LCM_Test.v" 420 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.779 ns ( 37.73 % ) " "Info: Total cell delay = 1.779 ns ( 37.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.936 ns ( 62.27 % ) " "Info: Total interconnect delay = 2.936 ns ( 62.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.715 ns" { H_Cont[10] always0~213 always0~215 always0~214 Tmp_DATA[7] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.715 ns" { H_Cont[10] always0~213 always0~215 always0~214 Tmp_DATA[7] } { 0.000ns 0.515ns 0.259ns 0.266ns 1.896ns } { 0.000ns 0.438ns 0.393ns 0.438ns 0.510ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl Tmp_DATA[7] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl Tmp_DATA[7] } { 0.000ns 1.091ns 1.026ns } { 0.000ns 0.000ns 0.537ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.614 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl H_Cont[10] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.614 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl H_Cont[10] } { 0.000ns 1.091ns 0.986ns } { 0.000ns 0.000ns 0.537ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.715 ns" { H_Cont[10] always0~213 always0~215 always0~214 Tmp_DATA[7] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.715 ns" { H_Cont[10] always0~213 always0~215 always0~214 Tmp_DATA[7] } { 0.000ns 0.515ns 0.259ns 0.266ns 1.896ns } { 0.000ns 0.438ns 0.393ns 0.438ns 0.510ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLOCK_50 register I2S_LCM_Config:u4\|I2S_Controller:u0\|mST\[4\] register sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[10\] 4.489 ns " "Info: Slack time is 4.489 ns for clock \"CLOCK_50\" between source register \"I2S_LCM_Config:u4\|I2S_Controller:u0\|mST\[4\]\" and destination register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[10\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "90.73 MHz 11.022 ns " "Info: Fmax is 90.73 MHz (period= 11.022 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "5.912 ns + Largest register register " "Info: + Largest register to register requirement is 5.912 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLOCK_50 20.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"CLOCK_50\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 10.000 ns " "Info: - Launch edge is 10.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLOCK_50 20.000 ns 10.000 ns inverted 50 " "Info: Clock period of Source clock \"CLOCK_50\" is 20.000 ns with inverted offset of 10.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.874 ns + Largest " "Info: + Largest clock skew is -3.874 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.698 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 2.698 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 3; CLK Node = 'CLOCK_50'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "D:/EDA/DE2_LCM_Test/DE2_LCM_Test.v" 174 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 1702 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 1702; COMB Node = 'CLOCK_50~clkctrl'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "D:/EDA/DE2_LCM_Test/DE2_LCM_Test.v" 174 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.044 ns) + CELL(0.537 ns) 2.698 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[10\] 3 REG LCFF_X32_Y18_N27 3 " "Info: 3: + IC(1.044 ns) + CELL(0.537 ns) = 2.698 ns; Loc. = LCFF_X32_Y18_N27; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[10\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.581 ns" { CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] } "NODE_NAME" } } { "../../altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "D:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" 834 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.93 % ) " "Info: Total cell delay = 1.536 ns ( 56.93 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.162 ns ( 43.07 % ) " "Info: Total interconnect delay = 1.162 ns ( 43.07 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.698 ns" { CLOCK_50 CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.698 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 6.572 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 6.572 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 3; CLK Node = 'CLOCK_50'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "D:/EDA/DE2_LCM_Test/DE2_LCM_Test.v" 174 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.477 ns) + CELL(0.787 ns) 3.263 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|mI2S_CLK 2 REG LCFF_X31_Y19_N15 3 " "Info: 2: + IC(1.477 ns) + CELL(0.787 ns) = 3.263 ns; Loc. = LCFF_X31_Y19_N15; Fanout = 3; REG Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|mI2S_CLK'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.264 ns" { CLOCK_50 I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/EDA/DE2_LCM_Test/I2S_Controller.v" 96 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.770 ns) + CELL(0.000 ns) 5.033 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|mI2S_CLK~clkctrl 3 COMB CLKCTRL_G8 30 " "Info: 3: + IC(1.770 ns) + CELL(0.000 ns) = 5.033 ns; Loc. = CLKCTRL_G8; Fanout = 30; COMB Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|mI2S_CLK~clkctrl'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.770 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/EDA/DE2_LCM_Test/I2S_Controller.v" 96 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.002 ns) + CELL(0.537 ns) 6.572 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|mST\[4\] 4 REG LCFF_X34_Y21_N17 9 " "Info: 4: + IC(1.002 ns) + CELL(0.537 ns) = 6.572 ns; Loc. = LCFF_X34_Y21_N17; Fanout = 9; REG Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|mST\[4\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.539 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mST[4] } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/EDA/DE2_LCM_Test/I2S_Controller.v" 138 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 35.35 % ) " "Info: Total cell delay = 2.323 ns ( 35.35 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.249 ns ( 64.65 % ) " "Info: Total interconnect delay = 4.249 ns ( 64.65 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.572 ns" { CLOCK_50 I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mST[4] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.572 ns" { CLOCK_50 CLOCK_50~combout I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mST[4] } { 0.000ns 0.000ns 1.477ns 1.770ns 1.002ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.698 ns" { CLOCK_50 CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.698 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.572 ns" { CLOCK_50 I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mST[4] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.572 ns" { CLOCK_50 CLOCK_50~combout I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mST[4] } { 0.000ns 0.000ns 1.477ns 1.770ns 1.002ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "I2S_Controller.v" "" { Text "D:/EDA/DE2_LCM_Test/I2S_Controller.v" 138 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" { } { { "../../altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "D:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" 834 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.698 ns" { CLOCK_50 CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.698 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.572 ns" { CLOCK_50 I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mST[4] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.572 ns" { CLOCK_50 CLOCK_50~combout I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mST[4] } { 0.000ns 0.000ns 1.477ns 1.770ns 1.002ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.423 ns - Longest register register " "Info: - Longest register to register delay is 1.423 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|mST\[4\] 1 REG LCFF_X34_Y21_N17 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X34_Y21_N17; Fanout = 9; REG Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|mST\[4\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { I2S_LCM_Config:u4|I2S_Controller:u0|mST[4] } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "D:/EDA/DE2_LCM_Test/I2S_Controller.v" 138 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.057 ns) + CELL(0.366 ns) 1.423 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[10\] 2 REG LCFF_X32_Y18_N27 3 " "Info: 2: + IC(1.057 ns) + CELL(0.366 ns) = 1.423 ns; Loc. = LCFF_X32_Y18_N27; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|acq_trigger_in_reg\[10\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.423 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|mST[4] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] } "NODE_NAME" } } { "../../altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "D:/altera/71/quartus/libraries/megafunctions/sld_signaltap.vhd" 834 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.366 ns ( 25.72 % ) " "Info: Total cell delay = 0.366 ns ( 25.72 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.057 ns ( 74.28 % ) " "Info: Total interconnect delay = 1.057 ns ( 74.28 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.423 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|mST[4] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.423 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|mST[4] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] } { 0.000ns 1.057ns } { 0.000ns 0.366ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.698 ns" { CLOCK_50 CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.698 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] } { 0.000ns 0.000ns 0.118ns 1.044ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.572 ns" { CLOCK_50 I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mST[4] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.572 ns" { CLOCK_50 CLOCK_50~combout I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mST[4] } { 0.000ns 0.000ns 1.477ns 1.770ns 1.002ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.423 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|mST[4] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.423 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|mST[4] sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[10] } { 0.000ns 1.057ns } { 0.000ns 0.366ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
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