📄 decode_4oa.tdf
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--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_DECODES=4 LPM_WIDTH=2 data enable eq
--VERSION_BEGIN 7.1 cbx_cycloneii 2007:01:23:09:39:40:SJ cbx_lpm_add_sub 2007:01:08:11:15:18:SJ cbx_lpm_compare 2007:02:05:11:33:54:SJ cbx_lpm_decode 2006:11:21:10:27:00:SJ cbx_mgl 2007:04:03:14:06:46:SJ cbx_stratix 2007:04:12:16:43:52:SJ cbx_stratixii 2007:02:12:17:08:26:SJ VERSION_END
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--synthesis_resources = lut 4
SUBDESIGN decode_4oa
(
data[1..0] : input;
enable : input;
eq[3..0] : output;
)
VARIABLE
data_wire[1..0] : WIRE;
enable_wire : WIRE;
eq_node[3..0] : WIRE;
eq_wire[3..0] : WIRE;
w_anode691w[2..0] : WIRE;
w_anode704w[2..0] : WIRE;
w_anode712w[2..0] : WIRE;
w_anode720w[2..0] : WIRE;
BEGIN
data_wire[] = data[];
enable_wire = enable;
eq[] = eq_node[];
eq_node[3..0] = eq_wire[3..0];
eq_wire[] = ( w_anode720w[2..2], w_anode712w[2..2], w_anode704w[2..2], w_anode691w[2..2]);
w_anode691w[] = ( (w_anode691w[1..1] & (! data_wire[1..1])), (w_anode691w[0..0] & (! data_wire[0..0])), enable_wire);
w_anode704w[] = ( (w_anode704w[1..1] & (! data_wire[1..1])), (w_anode704w[0..0] & data_wire[0..0]), enable_wire);
w_anode712w[] = ( (w_anode712w[1..1] & data_wire[1..1]), (w_anode712w[0..0] & (! data_wire[0..0])), enable_wire);
w_anode720w[] = ( (w_anode720w[1..1] & data_wire[1..1]), (w_anode720w[0..0] & data_wire[0..0]), enable_wire);
END;
--VALID FILE
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