altsyncram_q1l1.tdf

基于Quartus的TFT－LCD测试程序

			PORT_A_FIRST_BIT_NUMBER = 35,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 44,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 35,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 44,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a36 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 36,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 44,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 36,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 44,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a37 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 37,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 44,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 37,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 44,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a38 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 38,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 44,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 38,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 44,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a39 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 39,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 44,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 39,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 44,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a40 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 40,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 44,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 40,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 44,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a41 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 41,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 44,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 41,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 44,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a42 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 42,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 44,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 42,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 44,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a43 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 8,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 43,
			PORT_A_LAST_ADDRESS = 255,
			PORT_A_LOGICAL_RAM_DEPTH = 256,
			PORT_A_LOGICAL_RAM_WIDTH = 44,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 8,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 43,
			PORT_B_LAST_ADDRESS = 255,
			PORT_B_LOGICAL_RAM_DEPTH = 256,
			PORT_B_LOGICAL_RAM_WIDTH = 44,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	address_a_wire[7..0]	: WIRE;
	address_b_wire[7..0]	: WIRE;

BEGIN 
	ram_block2a[43..0].clk0 = clock0;
	ram_block2a[43..0].clk1 = clock1;
	ram_block2a[43..0].ena0 = clocken0;
	ram_block2a[43..0].ena1 = clocken1;
	ram_block2a[43..0].portaaddr[] = ( address_a_wire[7..0]);
	ram_block2a[0].portadatain[] = ( data_a[0..0]);
	ram_block2a[1].portadatain[] = ( data_a[1..1]);
	ram_block2a[2].portadatain[] = ( data_a[2..2]);
	ram_block2a[3].portadatain[] = ( data_a[3..3]);
	ram_block2a[4].portadatain[] = ( data_a[4..4]);
	ram_block2a[5].portadatain[] = ( data_a[5..5]);
	ram_block2a[6].portadatain[] = ( data_a[6..6]);
	ram_block2a[7].portadatain[] = ( data_a[7..7]);
	ram_block2a[8].portadatain[] = ( data_a[8..8]);
	ram_block2a[9].portadatain[] = ( data_a[9..9]);
	ram_block2a[10].portadatain[] = ( data_a[10..10]);
	ram_block2a[11].portadatain[] = ( data_a[11..11]);
	ram_block2a[12].portadatain[] = ( data_a[12..12]);
	ram_block2a[13].portadatain[] = ( data_a[13..13]);
	ram_block2a[14].portadatain[] = ( data_a[14..14]);
	ram_block2a[15].portadatain[] = ( data_a[15..15]);
	ram_block2a[16].portadatain[] = ( data_a[16..16]);
	ram_block2a[17].portadatain[] = ( data_a[17..17]);
	ram_block2a[18].portadatain[] = ( data_a[18..18]);
	ram_block2a[19].portadatain[] = ( data_a[19..19]);
	ram_block2a[20].portadatain[] = ( data_a[20..20]);
	ram_block2a[21].portadatain[] = ( data_a[21..21]);
	ram_block2a[22].portadatain[] = ( data_a[22..22]);
	ram_block2a[23].portadatain[] = ( data_a[23..23]);
	ram_block2a[24].portadatain[] = ( data_a[24..24]);
	ram_block2a[25].portadatain[] = ( data_a[25..25]);
	ram_block2a[26].portadatain[] = ( data_a[26..26]);
	ram_block2a[27].portadatain[] = ( data_a[27..27]);
	ram_block2a[28].portadatain[] = ( data_a[28..28]);
	ram_block2a[29].portadatain[] = ( data_a[29..29]);
	ram_block2a[30].portadatain[] = ( data_a[30..30]);
	ram_block2a[31].portadatain[] = ( data_a[31..31]);
	ram_block2a[32].portadatain[] = ( data_a[32..32]);
	ram_block2a[33].portadatain[] = ( data_a[33..33]);
	ram_block2a[34].portadatain[] = ( data_a[34..34]);
	ram_block2a[35].portadatain[] = ( data_a[35..35]);
	ram_block2a[36].portadatain[] = ( data_a[36..36]);
	ram_block2a[37].portadatain[] = ( data_a[37..37]);
	ram_block2a[38].portadatain[] = ( data_a[38..38]);
	ram_block2a[39].portadatain[] = ( data_a[39..39]);
	ram_block2a[40].portadatain[] = ( data_a[40..40]);
	ram_block2a[41].portadatain[] = ( data_a[41..41]);
	ram_block2a[42].portadatain[] = ( data_a[42..42]);
	ram_block2a[43].portadatain[] = ( data_a[43..43]);
	ram_block2a[43..0].portawe = wren_a;
	ram_block2a[43..0].portbaddr[] = ( address_b_wire[7..0]);
	ram_block2a[0].portbdatain[] = ( data_b[0..0]);
	ram_block2a[1].portbdatain[] = ( data_b[1..1]);
	ram_block2a[2].portbdatain[] = ( data_b[2..2]);
	ram_block2a[3].portbdatain[] = ( data_b[3..3]);
	ram_block2a[4].portbdatain[] = ( data_b[4..4]);
	ram_block2a[5].portbdatain[] = ( data_b[5..5]);
	ram_block2a[6].portbdatain[] = ( data_b[6..6]);
	ram_block2a[7].portbdatain[] = ( data_b[7..7]);
	ram_block2a[8].portbdatain[] = ( data_b[8..8]);
	ram_block2a[9].portbdatain[] = ( data_b[9..9]);
	ram_block2a[10].portbdatain[] = ( data_b[10..10]);
	ram_block2a[11].portbdatain[] = ( data_b[11..11]);
	ram_block2a[12].portbdatain[] = ( data_b[12..12]);
	ram_block2a[13].portbdatain[] = ( data_b[13..13]);
	ram_block2a[14].portbdatain[] = ( data_b[14..14]);
	ram_block2a[15].portbdatain[] = ( data_b[15..15]);
	ram_block2a[16].portbdatain[] = ( data_b[16..16]);
	ram_block2a[17].portbdatain[] = ( data_b[17..17]);
	ram_block2a[18].portbdatain[] = ( data_b[18..18]);
	ram_block2a[19].portbdatain[] = ( data_b[19..19]);
	ram_block2a[20].portbdatain[] = ( data_b[20..20]);
	ram_block2a[21].portbdatain[] = ( data_b[21..21]);
	ram_block2a[22].portbdatain[] = ( data_b[22..22]);
	ram_block2a[23].portbdatain[] = ( data_b[23..23]);
	ram_block2a[24].portbdatain[] = ( data_b[24..24]);
	ram_block2a[25].portbdatain[] = ( data_b[25..25]);
	ram_block2a[26].portbdatain[] = ( data_b[26..26]);
	ram_block2a[27].portbdatain[] = ( data_b[27..27]);
	ram_block2a[28].portbdatain[] = ( data_b[28..28]);
	ram_block2a[29].portbdatain[] = ( data_b[29..29]);
	ram_block2a[30].portbdatain[] = ( data_b[30..30]);
	ram_block2a[31].portbdatain[] = ( data_b[31..31]);
	ram_block2a[32].portbdatain[] = ( data_b[32..32]);
	ram_block2a[33].portbdatain[] = ( data_b[33..33]);
	ram_block2a[34].portbdatain[] = ( data_b[34..34]);
	ram_block2a[35].portbdatain[] = ( data_b[35..35]);
	ram_block2a[36].portbdatain[] = ( data_b[36..36]);
	ram_block2a[37].portbdatain[] = ( data_b[37..37]);
	ram_block2a[38].portbdatain[] = ( data_b[38..38]);
	ram_block2a[39].portbdatain[] = ( data_b[39..39]);
	ram_block2a[40].portbdatain[] = ( data_b[40..40]);
	ram_block2a[41].portbdatain[] = ( data_b[41..41]);
	ram_block2a[42].portbdatain[] = ( data_b[42..42]);
	ram_block2a[43].portbdatain[] = ( data_b[43..43]);
	ram_block2a[43..0].portbrewe = wren_b;
	address_a_wire[] = address_a[];
	address_b_wire[] = address_b[];
	q_a[] = ( ram_block2a[43..0].portadataout[0..0]);
	q_b[] = ( ram_block2a[43..0].portbdataout[0..0]);
END;
--VALID FILE