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📄 altsyncram_i4l1.tdf

📁 基于Quartus的TFT－LCD测试程序
💻 TDF
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			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 2047,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 55,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 11,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 10,
			PORT_B_LAST_ADDRESS = 2047,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 55,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a11 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 11,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 2047,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 55,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 11,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 11,
			PORT_B_LAST_ADDRESS = 2047,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 55,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a12 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 11,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 12,
			PORT_A_LAST_ADDRESS = 2047,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 55,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 11,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 12,
			PORT_B_LAST_ADDRESS = 2047,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 55,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a13 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 11,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 13,
			PORT_A_LAST_ADDRESS = 2047,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 55,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 11,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 13,
			PORT_B_LAST_ADDRESS = 2047,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 55,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a14 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 11,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 14,
			PORT_A_LAST_ADDRESS = 2047,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 55,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 11,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 14,
			PORT_B_LAST_ADDRESS = 2047,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 55,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a15 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 11,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 15,
			PORT_A_LAST_ADDRESS = 2047,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 55,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 11,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 15,
			PORT_B_LAST_ADDRESS = 2047,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 55,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a16 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 11,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 16,
			PORT_A_LAST_ADDRESS = 2047,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 55,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 11,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 16,
			PORT_B_LAST_ADDRESS = 2047,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 55,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a17 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 11,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 17,
			PORT_A_LAST_ADDRESS = 2047,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 55,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 11,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 17,
			PORT_B_LAST_ADDRESS = 2047,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 55,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a18 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 11,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 18,
			PORT_A_LAST_ADDRESS = 2047,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 55,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 11,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 18,
			PORT_B_LAST_ADDRESS = 2047,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 55,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a19 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 11,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 19,
			PORT_A_LAST_ADDRESS = 2047,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 55,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 11,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 19,
			PORT_B_LAST_ADDRESS = 2047,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 55,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a20 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 11,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 20,
			PORT_A_LAST_ADDRESS = 2047,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 55,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 11,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 20,
			PORT_B_LAST_ADDRESS = 2047,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 55,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a21 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 11,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 21,
			PORT_A_LAST_ADDRESS = 2047,
			PORT_A_LOGICAL_RAM_DEPTH = 2048,
			PORT_A_LOGICAL_RAM_WIDTH = 55,
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 11,
			PORT_B_DATA_IN_CLOCK = "clock1",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 21,
			PORT_B_LAST_ADDRESS = 2047,
			PORT_B_LOGICAL_RAM_DEPTH = 2048,
			PORT_B_LOGICAL_RAM_WIDTH = 55,
			PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block2a22 : cycloneii_ram_block
		WITH (
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "bidir_dual_port",
			PORT_A_ADDRESS_WIDTH = 11,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
			PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 22,
			PORT_A_LAST_ADDRESS = 2047,
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