📄 sipoctl10b_bram_v2_virtex5.vhd
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-------------------------------------------------------------------------------
-- Module: sipoCtl10b_BRAM_v2
-------------------------------------------------------------------------------
--**************************************************************************
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--**************************************************************************
-------------------------------------------------------------------------------
-- Filename: sipoCtl10b_BRAM_v2.vhd
--
-- Description:
--
-- This module takes in 0 to 10 bits each cycle and control the data
-- select mux and write enable control lines for each storage elements.
--
-- The output of this module control storage elements 0 to 4.
--
-- Design Notes:
-- 1. This version is for Virtex-5 devices.
-- 2.
-- 3.
-------------------------------------------------------------------------------
-- Owners: Jerry Chuang
-- Revision: 1.0
--
-- Modification History:
-- Date Init Description
-- --------- ------ --------------------------------------------------------
-- 08/10/2004 JC Initial Release
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library unisim;
use unisim.vcomponents.all;
use work.PKG_XILINX.all;
use work.PKG_OVERSAMP.all;
-----------------------------------------------------------------
entity sipoCtl10b_BRAM_v2 is
port(
-- Port A
A_rst : in std_logic;
A_clk : in std_logic;
A_en : in std_logic;
A_valid : in std_logic_vector(3 downto 0); -- Number of valid bits
A_bankSel : out std_logic; -- '0' select bank0 read from, '1' select bank1
A_byteRdy : out std_logic; -- Byte Ready
A_bitSel : out lv4_array(1 downto 0); -- Select which bit the storage element should use
A_we : out lv2_array(9 downto 0); -- Select which FF should be enabled
-- Port B
B_rst : in std_logic;
B_clk : in std_logic;
B_en : in std_logic;
B_valid : in std_logic_vector(3 downto 0);
B_bankSel : out std_logic;
B_byteRdy : out std_logic;
B_bitSel : out lv4_array(1 downto 0);
B_we : out lv2_array(9 downto 0)
);
end sipoCtl10b_BRAM_v2;
-----------------------------------------------------------------
architecture rtl of sipoCtl10b_BRAM_v2 is
signal zero32 : std_logic_vector(31 downto 0);
signal zero4 : std_logic_vector( 3 downto 0);
signal A_ad : std_logic_vector( 8 downto 0);
signal A_do : std_logic_vector(31 downto 0);
signal A_dop : std_logic_vector( 3 downto 0);
signal A_addr : std_logic_vector(15 downto 0);
signal B_ad : std_logic_vector( 8 downto 0);
signal B_do : std_logic_vector(31 downto 0);
signal B_dop : std_logic_vector( 3 downto 0);
signal B_addr : std_logic_vector(15 downto 0);
begin
zero32 <= (others => '0');
zero4 <= (others => '0');
--
-- Side A Configuration
--
A_ad <= A_do(31) & A_dop & A_valid;
A_addr <= "00" & A_ad & "00000";
A_bankSel <= A_do(31);
A_byteRdy <= A_do(30);
A_bitSel(0) <= A_do(23 downto 20);
A_bitSel(1) <= A_do(27 downto 24);
P_A_OUT_0TO9 : process( A_do )
begin
for i in 0 to 9 loop
A_we(i) <= A_do(i*2+1 downto i*2);
end loop;
end process;
--
-- Side B Configuration
--
B_ad <= B_do(31) & B_dop & B_valid;
B_addr <= "00" & B_ad & "00000";
B_bankSel <= B_do(31);
B_byteRdy <= B_do(30);
B_bitSel(0) <= B_do(23 downto 20);
B_bitSel(1) <= B_do(27 downto 24);
P_B_OUT_0TO9 : process( B_do )
begin
for i in 0 to 9 loop
B_we(i) <= B_do(i*2+1 downto i*2);
end loop;
end process;
--------------------------------------------------------------------------------------------------
-- BRAM Instantiations
--------------------------------------------------------------------------------------------------
C_BRAMSIPO_0TO9 : RAMB36
generic map(
DOA_REG => 0,
DOB_REG => 0,
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36,
INIT_00 => X"C1655502C0555402C9455002C8354002C7250002C6140002C500000204900000",
INIT_01 => X"0000000000000000000000000000000000000000C4955556C3855552C2755542",
INIT_02 => X"C055540AC945500AC835400AC725000AC614000AC500000A0490000803800000",
INIT_03 => X"0000000000000000000000000000000000000000C385555AC275554AC165550A",
INIT_04 => X"C945502AC835402AC725002AC614002AC500002A049000280380002002700000",
INIT_05 => X"0000000000000000000000000000000000000000C275556AC165552AC055542A",
INIT_06 => X"C83540AAC72500AAC61400AAC50000AA049000A8038000A00270008001600000",
INIT_07 => X"0000000000000000000000000000000000000000C16555AAC05554AAC94550AA",
INIT_08 => X"C72502AAC61402AAC50002AA049002A8038002A0027002800160020000500000",
INIT_09 => X"0000000000000000000000000000000000000000C05556AAC94552AAC83542AA",
INIT_0A => X"C6140AAAC5000AAA04900AA803800AA002700A8001600A000050080009400000",
INIT_0B => X"0000000000000000000000000000000000000000C9455AAAC8354AAAC7250AAA",
INIT_0C => X"C5002AAA04902AA803802AA002702A8001602A00005028000940200008300000",
INIT_0D => X"0000000000000000000000000000000000000000C8356AAAC7252AAAC6142AAA",
INIT_0E => X"0490AAA80380AAA00270AA800160AA000050A8000940A0000830800007200000",
INIT_0F => X"0000000000000000000000000000000000000000C725AAAAC614AAAAC500AAAA",
INIT_10 => X"0382AAA00272AA800162AA000052A8000942A000083280000722000006100000",
INIT_11 => X"0000000000000000000000000000000000000000C616AAAAC502AAAA0492AAA8",
INIT_12 => X"027AAA80016AAA00005AA800094AA000083A8000072A00000618000005000000",
INIT_13 => X"0000000000000000000000000000000000000000C50AAAAA049AAAA8038AAAA0",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"416AAA01405AA801494AA001483A8001472A0001461800014500000184900000",
INIT_21 => X"0000000000000000000000000000000000000000449AAAA9438AAAA1427AAA81",
INIT_22 => X"405AA805494AA005483A8005472A000546180005450000058490000483800000",
INIT_23 => X"0000000000000000000000000000000000000000438AAAA5427AAA85416AAA05",
INIT_24 => X"494AA015483A8015472A00154618001545000015849000148380001082700000",
INIT_25 => X"0000000000000000000000000000000000000000427AAA95416AAA15405AA815",
INIT_26 => X"483A8055472A0055461800554500005584900054838000508270004081600000",
INIT_27 => X"0000000000000000000000000000000000000000416AAA55405AA855494AA055",
INIT_28 => X"472A015546180155450001558490015483800150827001408160010080500000",
INIT_29 => X"0000000000000000000000000000000000000000405AA955494AA155483A8155",
INIT_2A => X"4618055545000555849005548380055082700540816005008050040089400000",
INIT_2B => X"0000000000000000000000000000000000000000494AA555483A8555472A0555",
INIT_2C => X"4500155584901554838015508270154081601500805014008940100088300000",
INIT_2D => X"0000000000000000000000000000000000000000483A9555472A155546181555",
INIT_2E => X"8490555483805550827055408160550080505400894050008830400087200000",
INIT_2F => X"0000000000000000000000000000000000000000472A55554618555545005555",
INIT_30 => X"8381555082715540816155008051540089415000883140008721000086100000",
INIT_31 => X"0000000000000000000000000000000000000000461955554501555584915554",
INIT_32 => X"8275554081655500805554008945500088354000872500008614000085000000",
INIT_33 => X"0000000000000000000000000000000000000000450555558495555483855550",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_00 => X"0000034567890123000002345678901200000123456789010000001234567890",
INITP_01 => X"0000078901234567000006789012345600000567890123450000045678901234",
INITP_02 => X"0000000000000000000000000000000000000901234567890000089012345678",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000034567890123000002345678901200000123456789010000001234567890",
INITP_05 => X"0000078901234567000006789012345600000567890123450000045678901234",
INITP_06 => X"0000000000000000000000000000000000000901234567890000089012345678",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map(
SSRA => A_rst,
CLKA => A_clk,
ENA => A_en,
ADDRA => A_addr,
DOA => A_do,
DOPA => A_dop,
SSRB => B_rst,
CLKB => B_clk,
ENB => B_en,
ADDRB => B_addr,
DOB => B_do,
DOPB => B_dop,
-- Not used
DIA => zero32,
DIB => zero32,
DIPA => zero4,
DIPB => zero4,
REGCEA=> '1',
REGCEB=> '1',
WEA => "0000",
WEB => "0000",
CASCADEOUTLATA => open,
CASCADEOUTLATB => open,
CASCADEOUTREGA => open,
CASCADEOUTREGB => open,
CASCADEINLATA => '0',
CASCADEINLATB => '0',
CASCADEINREGA => '0',
CASCADEINREGB => '0'
);
end rtl;
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