📄 osdeci20b_48_1011x_bram.vhd
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-------------------------------------------------------------------------------
-- Module: osDeci20b_48_1011x_BRAM.vhd
-------------------------------------------------------------------------------
--**************************************************************************
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE.
--
-- (c) Copyright 2004 Xilinx, Inc.
-- All rights reserved.
--
--**************************************************************************
-------------------------------------------------------------------------------
-- Filename: osDeci20b_48_1011x_BRAM.vhd
--
-- Description:
--
-- This module is designed for 4/8/10/11X oversampling with 20b input from SERDES.
--
-- Design Notes:
-- 1.
-- 2.
-- 3.
-------------------------------------------------------------------------------
-- Owners: Jerry Chuang
-- Revision: 1.0
--
-- Modification History:
-- Date Init Description
-- --------- ------ --------------------------------------------------------
-- 03/16/2005 JC Initial Release
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------
entity osDeci20b_48_1011x_BRAM is
port(
A_rst : in std_logic;
A_clk : in std_logic;
A_en : in std_logic;
A_mode : in std_logic_vector(1 downto 0); -- 4/8/10/11X
A_edge : in std_logic_vector(3 downto 0); -- Edge Info bits
A_valid : out std_logic_vector(3 downto 0); -- Valid bits
A_dSel : out std_logic_vector(3 downto 0); -- Data Mux
B_rst : in std_logic;
B_clk : in std_logic;
B_en : in std_logic;
B_mode : in std_logic_vector(1 downto 0);
B_edge : in std_logic_vector(3 downto 0);
B_valid : out std_logic_vector(3 downto 0);
B_dSel : out std_logic_vector(3 downto 0)
);
end osDeci20b_48_1011x_BRAM;
--------------------------------------------------------------------
architecture rtl of osDeci20b_48_1011x_BRAM is
signal zero1 : std_logic_vector( 0 downto 0);
signal A_ad : std_logic_vector(10 downto 0);
signal A_do : std_logic_vector( 7 downto 0);
signal A_dop : std_logic_vector( 0 downto 0);
signal B_ad : std_logic_vector(10 downto 0);
signal B_do : std_logic_vector( 7 downto 0);
signal B_dop : std_logic_vector( 0 downto 0);
begin
zero1(0) <= '0';
--
-- Side A Configuration
--
A_ad <= A_mode & A_dop & A_do(3 downto 0) & A_edge;
A_valid <= A_do(7 downto 4);
A_dSel <= A_do(3 downto 0);
--
-- Side B Configuration
--
B_ad <= B_mode & B_dop & B_do(3 downto 0) & B_edge;
B_valid <= B_do(7 downto 4);
B_dSel <= B_do(3 downto 0);
--------------------------------------------------------------------------------------------------
-- BRAM Instantiations
--------------------------------------------------------------------------------------------------
C_BRAMOSDECI5 : RAMB16_S9_S9
generic map(
INIT_00 => X"5151505051515050515150505353515150435043504352505043504350435250",
INIT_01 => X"5353536153535361525252535252525352525252515151515260526051525152",
INIT_02 => X"5151515151515151515151515151515151515151515151515151515151515151",
INIT_03 => X"5151515151515151515151515151515151515151515151515151515151515151",
INIT_04 => X"5151515151515151515151515151515151515151515151515151515151515151",
INIT_05 => X"5151515151515151515151515151515151515151515151515151515151515151",
INIT_06 => X"5151515151515151515151515151515151515151515151515151515151515151",
INIT_07 => X"5151515151515151515151515151515151515151515151515151515151515151",
INIT_08 => X"5151514352525251515151435252525150505151505051515042515050425150",
INIT_09 => X"5360536053605360536053605153515352525252525250505353535353535252",
INIT_0A => X"5151515151515151515151515151515151515151515151515151515151515151",
INIT_0B => X"5151515151515151515151515151515151515151515151515151515151515151",
INIT_0C => X"5151515151515151515151515151515151515151515151515151515151515151",
INIT_0D => X"5151515151515151515151515151515151515151515151515151515151515151",
INIT_0E => X"5151515151515151515151515151515151515151515151515151515151515151",
INIT_0F => X"5151515151515151515151515151515151515151515151515151515151515151",
INIT_10 => X"2525252525252525242426262626252424242424242424242323232525252524",
INIT_11 => X"2727272727272727303030302726262626262626262626262527272727262525",
INIT_12 => X"3131313131313131323231303030323230303030303030303131313027272731",
INIT_13 => X"3333333333333333333232323434343432323232323232323332313131333333",
INIT_14 => X"3333333333333333333333333333333333333333333333333333333333333333",
INIT_15 => X"3333333333333333333333333333333333333333333333333333333333333333",
INIT_16 => X"3333333333333333333333333333333333333333333333333333333333333333",
INIT_17 => X"3333333333333333333333333333333333333333333333333333333333333333",
INIT_18 => X"2525252525252525242426262626252424242424242424242323232525252524",
INIT_19 => X"2727272727272727303030302726262626262626262626262527272727262525",
INIT_1A => X"3131313131313131323231303030323230303030303030303131313027272731",
INIT_1B => X"3333333333333333333232323434343432323232323232323332313131333333",
INIT_1C => X"3333333333333333333333333333333333333333333333333333333333333333",
INIT_1D => X"3333333333333333333333333333333333333333333333333333333333333333",
INIT_1E => X"3333333333333333333333333333333333333333333333333333333333333333",
INIT_1F => X"3333333333333333333333333333333333333333333333333333333333333333",
INIT_20 => X"2121212121212222222120202020222220202020202021212121201919191921",
INIT_21 => X"2323232323232423222222222424242422222222222223232221212121232323",
INIT_22 => X"2525252525252424242426262626262524242424242424232323232525252525",
INIT_23 => X"2727272727272626282828282827262626262626262625252527272727272625",
INIT_24 => X"2929292929293030303030292828282828282828282827292929292928272727",
INIT_25 => X"2424242424242424242424242424242424242424242424242424242424242424",
INIT_26 => X"2424242424242424242424242424242424242424242424242424242424242424",
INIT_27 => X"2424242424242424242424242424242424242424242424242424242424242424",
INIT_28 => X"2121212121212222222120202020222220202020202021212121201919191921",
INIT_29 => X"2323232323232423222222222424242422222222222223232221212121232323",
INIT_2A => X"2525252525252424242426262626262524242424242424232323232525252525",
INIT_2B => X"2727272727272626282828282827262626262626262625252527272727272625",
INIT_2C => X"2929292929293030303030292828282828282828282827292929292928272727",
INIT_2D => X"2424242424242424242424242424242424242424242424242424242424242424",
INIT_2E => X"2424242424242424242424242424242424242424242424242424242424242424",
INIT_2F => X"2424242424242424242424242424242424242424242424242424242424242424",
INIT_30 => X"1A1A1A1A1A20202020202019191919191919191919181A1A1A1A1A1A18181818",
INIT_31 => X"21212121212222222220202020202222202020202021212121211A1A1A1A1A21",
INIT_32 => X"2323232323242422222222222424242422222222222323232121212121232323",
INIT_33 => X"2525252525242424242426262626262624242424242523232323232525252525",
INIT_34 => X"2727272727262626282828282828262626262626262525252527272727272725",
INIT_35 => X"2525252525252525252525252525252528282828282727292929292929272727",
INIT_36 => X"2525252525252525252525252525252525252525252525252525252525252525",
INIT_37 => X"2525252525252525252525252525252525252525252525252525252525252525",
INIT_38 => X"1A1A1A1A1A20202020202019191919191919191919181A1A1A1A1A1A18181818",
INIT_39 => X"21212121212222222220202020202222202020202021212121211A1A1A1A1A21",
INIT_3A => X"2323232323242422222222222424242422222222222323232121212121232323",
INIT_3B => X"2525252525242424242426262626262624242424242523232323232525252525",
INIT_3C => X"2727272727262626282828282828262626262626262525252527272727272725",
INIT_3D => X"2525252525252525252525252525252528282828282727292929292929272727",
INIT_3E => X"2525252525252525252525252525252525252525252525252525252525252525",
INIT_3F => X"2525252525252525252525252525252525252525252525252525252525252525",
INITP_00 => X"00000000000000000000000000000000000000000000000011000050000C0202",
INITP_01 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5FCFFEFEFFFBB",
INITP_02 => X"00000000000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000000000000000000000000000",
INITP_04 => X"000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_05 => X"FFFFFFFFFFFFFFFFFFFFFFFF0000000000000000000000000000000000000000",
INITP_06 => X"00000000000000000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INITP_07 => X"FFFFFFFFFFFFFFFFFFFF00000000000000000000000000000000000000000000"
)
port map(
SSRA => A_rst,
CLKA => A_clk,
ENA => A_en,
ADDRA => A_ad,
DOA => A_do,
DOPA => A_dop,
SSRB => B_rst,
CLKB => B_clk,
ENB => B_en,
ADDRB => B_ad,
DOB => B_do,
DOPB => B_dop,
-- Not used
DIA => x"00",
DIB => x"00",
DIPA => zero1,
DIPB => zero1,
WEA => '0',
WEB => '0'
);
end rtl;
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