example_sdsdi_lvds_top.ucf

使用ＩＤＥＬＡＹ实现８倍过采样异步串行信号恢复信号

//------------------------------------------------------------------------------ 
// Copyright (c) 2006 Xilinx, Inc. 
// All Rights Reserved 
//------------------------------------------------------------------------------ 
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /   Vendor: Xilinx 
// \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
//  \   \        Filename: $RCSfile: example_sdsdi_lvds_top.ucf,rcs $
//  /   /        Date Last Modified:  $Date: 2006-09-22 13:59:58-06 $
// /___/   /\    Date Created: July 17, 2006 
// \   \  /  \ 
//  \___\/\___\ 
// 
//
// Revision History: 
// $Log: example_sdsdi_lvds_top.ucf,rcs $
// Revision 1.0  2006-09-22 13:59:58-06  jsnow
// Initial release.
//
//------------------------------------------------------------------------------ 
//
//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
//     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
//     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
//     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
//     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
//     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//
//------------------------------------------------------------------------------ 
//
// Timing constraints for the example_sdsdi_lvds_top file.
//
//------------------------------------------------------------------------------                                
#
# Clock Constraints
#

NET "PAD_clk_270M_p" TNM_NET = CLK270;
NET "PAD_clk_270M_n" TNM_NET = CLK270;
TIMESPEC TS_CLK270 = PERIOD CLK270 270 MHz HIGH 50 % INPUT_JITTER 70 ps;

#
# rx[1/2]_ce are the clock enable outputs from the data recovery unit (after
# going through a pipeline register). These clock enables throttle the 
# downstream logic, being clocked by the 270 MHz clock, to an effective clock 
# rate of 27 MHz. However, it is possible for the DRU to output data somewhat
# faster than 27 MHz because the data is being recovered asynchronously to the
# local 270 MHz reference clock, thus the timing constraint is set at 270 MHz /
# 9.
#
NET "rx1_ce" TNM = SDI_RX1_CE;
TIMESPEC TS_SDI_RX1_CE = FROM SDI_RX1_CE TO SDI_RX1_CE TS_CLK270/9;

NET "rx2_ce" TNM = SDI_RX2_CE;
TIMESPEC TS_SDI_RX2_CE = FROM SDI_RX2_CE TO SDI_RX2_CE TS_CLK270/9;

#
# The period<0> signal from each overampler controls the clock enable input to 
# the DRU. It is asserted one cycle out of every twenty of the 270 MHz clock. 
#
NET "OVRSAMPLE1/period<0>" TNM = DRU1_CE;
TIMESPEC TS_DRU1_CE = FROM DRU1_CE TO DRU1_CE TS_CLK270/20;

NET "OVRSAMPLE2/period<0>" TNM = DRU2_CE;
TIMESPEC TS_DRU2_CE = FROM DRU2_CE TO DRU2_CE TS_CLK270/20;

#
# Location constraints for the oversamplers and serial data inputs
# 
# These are device specific. The oversamplers must be constrained be immediately
# adjacent to the IOBs for the associated serial input data.
#
INST "OVRSAMPLE1" U_SET=USET_OVR1;
INST "OVRSAMPLE1" RLOC_ORIGIN = "X0Y24";

INST "OVRSAMPLE2" U_SET=USET_OVR2;
INST "OVRSAMPLE2" RLOC_ORIGIN = "X0Y18";

#
# Example location constraints for the SD-SDI LVDS inputs. These match the
# RLOC_ORIGIN constraints for the oversamplers in a Virtex-4 LX25 device in
# a SF363 package.
#
NET "PAD_sdsdi1_rxp" LOC = "R19";
NET "PAD_sdsdi1_rxn" LOC = "R20";

NET "PAD_sdsdi2_rxp" LOC = "T19";
NET "PAD_sdsdi2_rxn" LOC = "T20";