📄 example_sdsdi_lvds_top.vhd
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--------------------------------------------------------------------------------
-- Copyright (c) 2006 Xilinx, Inc.
-- All Rights Reserved
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
-- \ \ Filename: $RCSfile: example_sdsdi_lvds_top.vhd,rcs $
-- / / Date Last Modified: $Date: 2006-09-22 14:01:00-06 $
-- /___/ /\ Date Created: July 17, 2006
-- \ \ / \
-- \___\/\___\
--
--
-- Revision History:
-- $Log: example_sdsdi_lvds_top.vhd,rcs $
-- Revision 1.0 2006-09-22 14:01:00-06 jsnow
-- Initial release.
--
--------------------------------------------------------------------------------
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
-- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
-- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
-- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
-- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE.
--
--------------------------------------------------------------------------------
--
-- Description of module:
--
-- This is an example of using the IDELAY-based 8X oversampler to receive two
-- SD-SDI bitstreams at 270 Mbps.
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity example_sdsdi_lvds_top is
port (
-- Clock sources and clock source control signals
PAD_clk_200M_p: in std_logic; -- 200 MHz LVDS clock source
PAD_clk_200M_n: in std_logic;
PAD_clk_270M_p: in std_logic; -- 270 MHz LVDS clock source
PAD_clk_270M_n: in std_logic;
-- SDI Interface Data and Control Signals
PAD_sdsdi1_rxp: in std_logic; -- SD-SDI serial input LVDS pair #1
PAD_sdsdi1_rxn: in std_logic;
PAD_sdsdi2_rxp: in std_logic; -- SD-SDI serial input LVDS pair #2
PAD_sdsdi2_rxn: in std_logic;
-- Output Signals
PAD_clkout_p: out std_logic; -- 270 MHz clock output
PAD_clkout_n: out std_logic;
PAD_rx1_ce: out std_logic; -- Rx #1 clock enable
PAD_rx1_video: out std_logic_vector(9 downto 0); -- Rx #1 video data
PAD_rx2_ce: out std_logic; -- Rx #2 clock enable
PAD_rx2_video: out std_logic_vector(9 downto 0) -- Rx #2 video data
);
end example_sdsdi_lvds_top;
architecture synth of example_sdsdi_lvds_top is
-------------------------------------------------------------------------------
-- Signal definitions
--
-- Clock signals
signal clk_270M_in : std_logic; -- 270 MHz clock before DCM
signal dcm270_clk0 : std_logic; -- clk0 output of DCM270
signal dcm270_clk90 : std_logic; -- clk90 output of DCM270
signal gclk_270M : std_logic; -- global 270 MHz clock
signal gclk_270M_90 : std_logic; -- global 270 MHz clock shifted 90 deg.
signal clk_200M_in : std_logic; -- 200 MHz clock input
signal gclk_200M : std_logic; -- global 200 MHz clock
signal idly_rdy : std_logic; -- IDELAYCTRL ready signal
-- Signals for SD-SDI Rx #1
signal rx1_ce : std_logic; -- 27 MHz clock enable from DRU
signal rx1_ovrs_dout : std_logic_vector(19 downto 0); -- oversampler output
signal rx1_ovrs_rdy : std_logic; -- oversampler output ready
signal rx1_recdata : std_logic_vector(9 downto 0); -- recovered data from DRU
signal rx1_dscout : std_logic_vector(9 downto 0); -- SDI descrambler output
signal rx1_video : std_logic_vector(9 downto 0); -- SDI framer output
-- Signals for SD-SDI Rx #2
signal rx2_ce : std_logic; -- 27 MHz clock enable from DRU
signal rx2_ovrs_dout : std_logic_vector(19 downto 0); -- oversampler output
signal rx2_ovrs_rdy : std_logic; -- oversampler output ready
signal rx2_recdata : std_logic_vector(9 downto 0); -- recovered data from DRU
signal rx2_dscout : std_logic_vector(9 downto 0); -- SDI descrambler output
signal rx2_video : std_logic_vector(9 downto 0); -- SDI framer output
attribute RLOC : string;
attribute KEEP : string;
attribute RLOC of OVRSAMPLE1 : label is "X0Y0";
attribute RLOC of OVRSAMPLE2 : label is "X0Y0";
attribute KEEP of rx1_ce : signal is "TRUE";
attribute KEEP of rx2_ce : signal is "TRUE";
component oversample_8x
generic (
IDELAY_45_DEGREES : integer := 6);
port(
clk0: in std_logic;
clk90: in std_logic;
PAD_din_p: in std_logic;
PAD_din_n: in std_logic;
dout_rdy: out std_logic;
dout: out std_logic_vector(19 downto 0));
end component;
component os48_1011x20bTo10b_top2
port(
rst :in std_logic;
bitOrderDinLSB :in std_logic;
bitOrderDoutLSB:in std_logic;
A_recclk :in std_logic;
A_en :in std_logic;
A_mode :in std_logic_vector( 1 downto 0);
A_din20b :in std_logic_vector(19 downto 0);
A_dout10bEn :out std_logic;
A_dout10b :out std_logic_vector( 9 downto 0);
A_dout20bEn :out std_logic;
A_dout20b :out std_logic_vector(19 downto 0);
B_recclk :in std_logic;
B_en :in std_logic;
B_mode :in std_logic_vector( 1 downto 0);
B_din20b :in std_logic_vector(19 downto 0);
B_dout10bEn :out std_logic;
B_dout10b :out std_logic_vector( 9 downto 0);
B_dout20bEn :out std_logic;
B_dout20b :out std_logic_vector(19 downto 0));
end component;
component par_descrambler
port (
clk: in std_logic;
rst: in std_logic;
ld: in std_logic;
d: in std_logic_vector(9 downto 0);
q: out std_logic_vector(9 downto 0));
end component;
component par_framer
port (
clk: in std_logic;
rst: in std_logic;
ce: in std_logic;
d: in std_logic_vector(9 downto 0);
frame_en: in std_logic;
q: out std_logic_vector(9 downto 0);
trs: out std_logic;
nsp: out std_logic);
end component;
begin
--------------------------------------------------------------------------------
-- Clock input buffers and global clock buffers
--
--
-- The 200 MHz clock is used as a reference clock to the IDELAYCTRL.
--
IBUFCLK200 : IBUFGDS
generic map (
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE)
port map(
I => PAD_clk_200M_p,
IB => PAD_clk_200M_n,
O => clk_200M_in);
BUFG200M : BUFG
port map (
I => clk_200M_in,
O => gclk_200M);
--
-- IDELAYCTRL
--
DLYCTRL : IDELAYCTRL
port map (
REFCLK => gclk_200M,
RDY => idly_rdy,
RST => '0');
--
-- 270 MHz clock input, DCM, and global clock buffers
--
-- This DCM produces 0 degree and 90 degree phases of the 270 MHz input clock.
--
IBUFCLK270 : IBUFGDS
generic map (
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE)
port map (
I => PAD_clk_270M_p,
IB => PAD_clk_270M_n,
O => clk_270M_in);
DCM270 : DCM_ADV
generic map (
CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.000000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 3.7037,
CLKOUT_PHASE_SHIFT => "NONE",
DCM_AUTOCALIBRATION => TRUE,
DCM_PERFORMANCE_MODE => "MAX_SPEED",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "HIGH",
DUTY_CYCLE_CORRECTION => TRUE,
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE,
FACTORY_JF => X"F0F0")
port map (
CLKFB => gclk_270M,
CLKIN => clk_270M_in,
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => X"0000",
DWE => '0',
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
RST => '0',
CLKDV => open,
CLKFX => open,
CLKFX180 => open,
CLK0 => dcm270_clk0,
CLK2X => open,
CLK2X180 => open,
CLK90 => dcm270_clk90,
CLK180 => open,
CLK270 => open,
DO => open,
DRDY => open,
LOCKED => open,
PSDONE => open);
BUFG270M : BUFG
port map (
I => dcm270_clk0,
O => gclk_270M);
BUFG270M90 : BUFG
port map (
I => dcm270_clk90,
O => gclk_270M_90);
--------------------------------------------------------------------------------
--
-- SD-SDI Rx #1
--
--
-- 8X oversampler
--
OVRSAMPLE1 : oversample_8x
generic map (
IDELAY_45_DEGREES => 6)
port map (
clk0 => gclk_270M,
clk90 => gclk_270M_90,
PAD_din_p => PAD_sdsdi1_rxp,
PAD_din_n => PAD_sdsdi1_rxn,
dout_rdy => rx1_ovrs_rdy,
dout => rx1_ovrs_dout);
--
-- DRU
--
-- The DRU is dual ported, handling both SD-SDI channels.
--
DRU : os48_1011x20bTo10b_top2
port map (
rst => '0',
bitOrderDinLSB => '1',
bitOrderDoutLSB => '1',
A_recclk => gclk_270M,
A_en => rx1_ovrs_rdy,
A_mode => "01",
A_din20b => rx1_ovrs_dout,
A_dout10bEn => rx1_ce,
A_dout10b => rx1_recdata,
A_dout20bEn => open,
A_dout20b => open,
B_recclk => gclk_270M,
B_en => rx2_ovrs_rdy,
B_mode => "01",
B_din20b => rx2_ovrs_dout,
B_dout10bEn => rx2_ce,
B_dout10b => rx2_recdata,
B_dout20bEn => open,
B_dout20b => open);
--
-- Put KEEP attributes on the two clock enables from the DRU so that their
-- names are preserved and they can be referenced in the UCF file to develop
-- the multi-cycle timing constraints.
--
--
-- SD-SDI decoder
--
DSC1 : par_descrambler
port map (
clk => gclk_270M,
rst => '0',
ld => rx1_ce,
d => rx1_recdata,
q => rx1_dscout);
--
-- SD-SDI framer
--
FRM1 : par_framer
port map (
clk => gclk_270M,
rst => '0',
ce => rx1_ce,
d => rx1_dscout,
frame_en => '1',
q => rx1_video,
trs => open,
nsp => open);
PAD_rx1_video <= rx1_video;
PAD_rx1_ce <= rx1_ce;
--------------------------------------------------------------------------------
--
-- SD-SDI Rx #2
--
--
-- 8X oversampler
--
OVRSAMPLE2 : oversample_8x
generic map (
IDELAY_45_DEGREES => 6)
port map (
clk0 => gclk_270M,
clk90 => gclk_270M_90,
PAD_din_p => PAD_sdsdi2_rxp,
PAD_din_n => PAD_sdsdi2_rxn,
dout_rdy => rx2_ovrs_rdy,
dout => rx2_ovrs_dout);
--
-- Data recovery is done by the dual ported DRU instantiated as part of Rx #1.
--
--
-- SMPTE decoder
--
DSC2 : par_descrambler
port map (
clk => gclk_270M,
rst => '0',
ld => rx2_ce,
d => rx2_recdata,
q => rx2_dscout);
--
-- Framer
--
FRM2 : par_framer
port map (
clk => gclk_270M,
rst => '0',
ce => rx2_ce,
d => rx2_dscout,
frame_en => '1',
q => rx2_video,
trs => open,
nsp => open);
PAD_rx2_video <= rx2_video;
PAD_rx2_ce <= rx2_ce;
OBUF270 : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
I => gclk_270M,
O => PAD_clkout_p,
OB => PAD_clkout_n);
end synth;
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