oversample_8x.vhd

使用ＩＤＥＬＡＹ实现８倍过采样异步串行信号恢复信号

        
    b2FF : FDCPE
    port map (
        Q          => b2,
        C          => clk0,
        CE         => '1',
        CLR        => '0',
        D          => b1,
        PRE        => '0');

    b3FF : FDCPE
    port map (
        Q          => b3,
        C          => clk0,
        CE         => '1',
        CLR        => '0',
        D          => b2,
        PRE        => '0');

    --
    -- These 3 FFs provide the 90 degree sample point.
    --
    c1FF : FDCPE
    port map (
        Q          => c1,
        C          => clk90,
        CE         => '1',
        CLR        => '0',
        D          => sdat_0_dly,
        PRE        => '0');

    c2FF : FDCPE
    port map (    
        Q          => c2,
        C          => clk0,
        CE         => '1',
        CLR        => '0',
        D          => c1,
        PRE        => '0');

    c3FF : FDCPE 
    port map (
        Q          => c3,
        C          => clk0,
        CE         => '1',
        CLR        => '0',
        D          => c2,
        PRE        => '0');

    --
    -- These 3 FFs provide the 135 degree sample point.
    --
    d1FF : FDCPE
    port map (
        Q          => d1,
        C          => clk90,
        CE         => '1',
        CLR        => '0',
        D          => sdatb_45_dly,
        PRE        => '0');
        
    d2FF : FDCPE
    port map (
        Q          => d2,
        C          => clk0,
        CE         => '1',
        CLR        => '0',
        D          => d1,
        PRE        => '0');

    d3FF: FDCPE
    port map (
        Q          => d3,
        C          => clk0,
        CE         => '1',
        CLR        => '0',
        D          => d2,
        PRE        => '0');

    --
    -- These 3 FFs provide the 180 degree sample point.
    --
    e1FF : FDCPE
    port map (
        Q          => e1,
        C          => not clk0,
        CE         => '1',
        CLR        => '0',
        D          => sdat_0_dly,
        PRE        => '0');
        
    e2FF : FDCPE
    port map (
        Q          => e2,
        C          => not clk0,
        CE         => '1',
        CLR        => '0',
        D          => e1,
        PRE        => '0');

    e3FF : FDCPE
    port map (
        Q          => e3,
        C          => clk0,
        CE         => '1',
        CLR        => '0',
        D          => e2,
        PRE        => '0');

    --
    -- These 3 FFs provide the 225 degree sample point.
    --
    f1FF : FDCPE
    port map (
        Q          => f1,
        C          => not clk0,
        CE         => '1',
        CLR        => '0',
        D          => sdatb_45_dly,
        PRE        => '0');
        
    f2FF : FDCPE
    port map (
        Q          => f2,
        C          => not clk0,
        CE         => '1',
        CLR        => '0',
        D          => f1,
        PRE        => '0');

    f3FF : FDCPE
    port map (
        Q          => f3,
        C          => clk0,
        CE         => '1',
        CLR        => '0',
        D          => f2,
        PRE        => '0');

    --
    -- These 3 FFs provide the 270 degree sample point.
    --
    g1FF : FDCPE
    port map (
        Q          => g1,
        C          => not clk90,
        CE         => '1',
        CLR        => '0',
        D          => sdat_0_dly,
        PRE        => '0');
        
    g2FF : FDCPE
    port map (
        Q          => g2,
        C          => not clk0,
        CE         => '1',
        CLR        => '0',
        D          => g1,
        PRE        => '0');

    g3FF : FDCPE
    port map (
        Q          => g3,
        C          => clk0,
        CE         => '1',
        CLR        => '0',
        D          => g2,
        PRE        => '0');

    -- 
    -- These 3 FFs provide the 315 degree sample point.
    --
    h1FF : FDCPE
    port map (
        Q          => h1,
        C          => not clk90,
        CE         => '1',
        CLR        => '0',
        D          => sdatb_45_dly,
        PRE        => '0');
        
    h2FF : FDCPE
    port map (
        Q          => h2,
        C          => not clk0,
        CE         => '1',
        CLR        => '0',
        D          => h1,
        PRE        => '0');

    h3FF : FDCPE
    port map (
        Q          => h3,
        C          => clk0,
        CE         => '1',
        CLR        => '0',
        D          => h2,
        PRE        => '0');

    -- 
    -- Input stage vector assignment. All samples created from the 45 degree data 
    -- must be inverted to compensate for the fact that the 45 degree data is 
    -- inverted.
    --
    instage_dout <= (not h3 & g3 &  not f3 & e3 & not d3 & c3 & not b3 & a3);
                                                                                                                                            
    --
    -- 8-bit to 20-bit conversion
    --
    -- This logic takes the 8 samples produced by the input stage every rising edge
    -- of clk0 and saves up 5 consecutive sets of these samples to create two
    -- 20-bit sample output vectors.
    --
    process(clk0)
    begin
        if rising_edge(clk0) then
            period <= (period(3 downto 0) & period(4));
        end if;
    end process;

    process(clk0)
    begin
        if rising_edge(clk0) then
            if period(0) = '1' or period(3) = '1' then
                samples_0 <= instage_dout;
            end if;
        end if;
    end process;
        
    process(clk0)
    begin
        if rising_edge(clk0) then
            if period(1) = '1' or period(4) = '1' then
                samples_1 <= instage_dout;
            end if;
        end if;
    end process;

    process(clk0)
    begin
        if rising_edge(clk0) then
            if period(2) = '1' then
            samples_2 <= instage_dout;
            end if;
        end if;
    end process;

    process(clk0)
    begin
        if rising_edge(clk0) then
            if period(3) = '1' then
                dout <= (samples_2(3 downto 0) & samples_1 & samples_0);
            elsif period(0) = '1' then
                dout <= (samples_1 & samples_0 & samples_2(7 downto 4));
            end if;
        end if;
    end process;
                       
    --
    -- To provide the maximum amount of setup time into the DRU, the dout_rdy signal
    -- is asserted during the clock cycle just before dout is updated. Thus, the
    -- DRU takes the last data on the same clock edge on which dout is updated with
    -- new data.
    --
    process(clk0)
    begin
        if rising_edge(clk0) then
            dout_rdy <= period(4) or period(2);
        end if;
    end process;
                                                
end synth;