oversample_8x.vhd

使用ＩＤＥＬＡＹ实现８倍过采样异步串行信号恢复信号

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-- Copyright (c) 2006 Xilinx, Inc. 
-- All Rights Reserved 
-------------------------------------------------------------------------------- 
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /   Vendor: Xilinx 
-- \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
--  \   \        Filename: $RCSfile: oversample_8x.vhd,rcs $
--  /   /        Date Last Modified:  $Date: 2006-09-22 14:00:41-06 $
-- /___/   /\    Date Created: July 17, 2006
-- \   \  /  \ 
--  \___\/\___\ 
-- 
--
-- Revision History: 
-- $Log: oversample_8x.vhd,rcs $
-- Revision 1.0  2006-09-22 14:00:41-06  jsnow
-- Initial release.
--
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--   
--   XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" 
--   AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND 
--   SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, 
--   OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, 
--   APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION 
--   THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, 
--   AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE 
--   FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY 
--   WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE 
--   IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR 
--   REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF 
--   INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
--   FOR A PARTICULAR PURPOSE. 
--
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--
-- This is a single channel 8X oversampling data recovery unit using bit-rate
-- clocks. It requires two phases of a clock running at the bit rate and uses 
-- two IDELAY primitives to provide the 45 degree phase shifting of the serial 
-- data.
--
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library UNISIM;
use UNISIM.vcomponents.all;


entity oversample_8x is
generic (
    IDELAY_45_DEGREES : integer := 6);              -- Specifices the delay for a
                                                    -- 1/8 bit delay with IDELAY. 6 is
                                                    -- the correct value for 270 Mb/s.
port (
    clk0:       in  std_logic;                      -- bit rate clock
    clk90:      in  std_logic;                      -- clk0 delayed 90 degrees
    PAD_din_p:  in  std_logic;                      -- serial input data
    PAD_din_n:  in  std_logic;                      -- inverted serial input data
    dout_rdy:   out std_logic;                      -- output data ready
    dout:       out std_logic_vector(19 downto 0)   -- output data
);
end oversample_8x;

architecture synth of oversample_8x is

-------------------------------------------------------------------------------
-- Signal definitions
--
signal sdata_in :   std_logic;                              -- true output of IBUFDS_DIFF_OUT
signal sdata_inb :  std_logic;                              -- complementary output of IBUFDS_DIFF_OUT
signal sdat_0_dly : std_logic;                              -- 0 degree data from IDELAY
signal sdatb_45_dly:std_logic;                              -- 45 degree data from IDEALY
signal a1, a2, a3 : std_logic;                              -- 0 degree capture pipeline
signal b1, b2, b3 : std_logic;                              -- 45 degree capture pipeline
signal c1, c2, c3 : std_logic;                              -- 90 degree capture pipeline
signal d1, d2, d3 : std_logic;                              -- 135 degree capture pipeline
signal e1, e2, e3 : std_logic;                              -- 180 degree capture pipeline
signal f1, f2, f3 : std_logic;                              -- 225 degree capture pipeline
signal g1, g2, g3 : std_logic;                              -- 270 degree capture pipeline
signal h1, h2, h3 : std_logic;                              -- 315 degree capture pipeline
signal instage_dout:std_logic_vector(7 downto 0);           -- 8X oversampled data from input state
signal samples_0 :  std_logic_vector(7 downto 0) := X"00";  -- used to make 20-bit dout vector
signal samples_1 :  std_logic_vector(7 downto 0) := X"00";  -- used to make 20-bit dout vector
signal samples_2 :  std_logic_vector(7 downto 0) := X"00";  -- used to make 20-bit dout vector
signal period :     std_logic_vector(4 downto 0) := "00001";-- sequencer for 20-bit vector creation

--------------------------------------------------------------------------------
-- Attributes
--
attribute DIFF_TERM : string;
attribute KEEP : string;
attribute SHREG_EXTRACT : string;
attribute IOB : string;
attribute RLOC : string;
attribute EQUIVALENT_REGISTER_REMOVAL : string;

attribute DIFF_TERM of IBUFSDI : label is "TRUE";

attribute EQUIVALENT_REGISTER_REMOVAL of a1 : signal is "TRUE";
attribute EQUIVALENT_REGISTER_REMOVAL of a2 : signal is "TRUE";
attribute EQUIVALENT_REGISTER_REMOVAL of a3 : signal is "TRUE";
attribute EQUIVALENT_REGISTER_REMOVAL of c1 : signal is "TRUE";
attribute EQUIVALENT_REGISTER_REMOVAL of c2 : signal is "TRUE";
attribute EQUIVALENT_REGISTER_REMOVAL of c3 : signal is "TRUE";
attribute EQUIVALENT_REGISTER_REMOVAL of d1 : signal is "TRUE";
attribute EQUIVALENT_REGISTER_REMOVAL of d2 : signal is "TRUE";
attribute EQUIVALENT_REGISTER_REMOVAL of d3 : signal is "TRUE";
attribute EQUIVALENT_REGISTER_REMOVAL of e1 : signal is "TRUE";
attribute EQUIVALENT_REGISTER_REMOVAL of e2 : signal is "TRUE";
attribute EQUIVALENT_REGISTER_REMOVAL of e3 : signal is "TRUE";
attribute EQUIVALENT_REGISTER_REMOVAL of f1 : signal is "TRUE";
attribute EQUIVALENT_REGISTER_REMOVAL of f2 : signal is "TRUE";
attribute EQUIVALENT_REGISTER_REMOVAL of f3 : signal is "TRUE";
attribute EQUIVALENT_REGISTER_REMOVAL of g1 : signal is "TRUE";
attribute EQUIVALENT_REGISTER_REMOVAL of g2 : signal is "TRUE";
attribute EQUIVALENT_REGISTER_REMOVAL of g3 : signal is "TRUE";
attribute EQUIVALENT_REGISTER_REMOVAL of h1 : signal is "TRUE";
attribute EQUIVALENT_REGISTER_REMOVAL of h2 : signal is "TRUE";
attribute EQUIVALENT_REGISTER_REMOVAL of h3 : signal is "TRUE";

attribute SHREG_EXTRACT of a1 : signal is "NO";
attribute SHREG_EXTRACT of a2 : signal is "NO";
attribute SHREG_EXTRACT of a3 : signal is "NO";
attribute SHREG_EXTRACT of c1 : signal is "NO";
attribute SHREG_EXTRACT of c2 : signal is "NO";
attribute SHREG_EXTRACT of c3 : signal is "NO";
attribute SHREG_EXTRACT of d1 : signal is "NO";
attribute SHREG_EXTRACT of d2 : signal is "NO";
attribute SHREG_EXTRACT of d3 : signal is "NO";
attribute SHREG_EXTRACT of e1 : signal is "NO";
attribute SHREG_EXTRACT of e2 : signal is "NO";
attribute SHREG_EXTRACT of e3 : signal is "NO";
attribute SHREG_EXTRACT of f1 : signal is "NO";
attribute SHREG_EXTRACT of f2 : signal is "NO";
attribute SHREG_EXTRACT of f3 : signal is "NO";
attribute SHREG_EXTRACT of g1 : signal is "NO";
attribute SHREG_EXTRACT of g2 : signal is "NO";
attribute SHREG_EXTRACT of g3 : signal is "NO";
attribute SHREG_EXTRACT of h1 : signal is "NO";
attribute SHREG_EXTRACT of h2 : signal is "NO";
attribute SHREG_EXTRACT of h3 : signal is "NO";

attribute IOB of a1FF : label is "FALSE";
attribute RLOC of a1FF : label is "X1Y1";

attribute IOB of b1FF : label is "FALSE";
attribute RLOC of b1FF : label is "X1Y1";

attribute IOB of c1FF : label is "FALSE";
attribute RLOC of c1FF : label is "X1Y0";

attribute IOB of d1FF : label is "FALSE";
attribute RLOC of d1FF : label is "X1Y0";

attribute IOB of e1FF : label is "FALSE";
attribute RLOC of e1FF : label is "X0Y1";

attribute IOB of f1FF : label is "FALSE";
attribute RLOC of f1FF : label is "X0Y1";

attribute IOB of g1FF : label is "FALSE";
attribute RLOC of g1FF : label is "X0Y0";

attribute IOB of h1FF : label is "FALSE";
attribute RLOC of h1FF : label is "X0Y0";

attribute KEEP of period : signal is "TRUE";

begin

    --
    -- The IBUFDS_DIFF_OUT primitive provides both true and complementary outputs
    -- of an LVDS input pair.
    --
    IBUFSDI : IBUFDS_DIFF_OUT 
    generic map (
        IOSTANDARD  => "LVDS_25")
    port map (
        I           => PAD_din_p,
        IB          => PAD_din_n,
        O           => sdata_in,
        OB          => sdata_inb);

    --
    -- IDELAY primitives
    --
    -- Two IDELAY primitives are used to create two phases of the data, one delayed
    -- 45 degrees relative to the other. Note that IDELAY block with 0 delay
    -- actually provides the data delayed by 45 degrees relative to the output
    -- of the other IDELAY block because the IDELAY primitive with the higher
    -- delay is providing older data. Also note that the 45 degree delayed data
    -- is inverted. This inversion is correct at the output of this module.
    --
    IDLY : IDELAY
    generic map (
        IOBDELAY_TYPE  => "FIXED",
        IOBDELAY_VALUE => IDELAY_45_DEGREES)
    port map (
        O       => sdat_0_dly,
        C       => '0',
        CE      => '0',
        I       => sdata_in,
        INC     => '0',
        RST     => '0');

    IDLYB : IDELAY 
    generic map (
        IOBDELAY_TYPE  => "FIXED",
        IOBDELAY_VALUE => 0)
    port map (
        O       => sdatb_45_dly,
        C       => '0',
        CE      => '0',
        I       => sdata_inb,
        INC     => '0',
        RST     => '0');

    --
    -- Data capture flip flops
    --
    -- These FFs sample the data and transfer all samples into a common clock 
    -- domain -- the rising edge of the clk0 phase.
    --
    -- All FFs are instantiated as FF primitives so that they can be easily RLOCed
    -- relative to each other to keep routing delay and skew to a minimum.
    --

    --
    -- These 3 FFs provide the 0 degree sample point.
    --
    a1FF : FDCPE
    port map (
        
        Q          => a1,
        C          => clk0,
        CE         => '1',
        CLR        => '0',
        D          => sdat_0_dly,
        PRE        => '0');

    a2FF : FDCPE
    port map (    
        Q          => a2,
        C          => clk0,
        CE         => '1',
        CLR        => '0',
        D          => a1,
        PRE        => '0');

    a3FF : FDCPE
    port map (
        Q          => a3,
        C          => clk0,
        CE         => '1',
        CLR        => '0',
        D          => a2,
        PRE        => '0');

    -- 
    -- These 3 FFs provide the 45 degree sample point.
    --
    b1FF : FDCPE 
    port map (
        Q          => b1,
        C          => clk0,
        CE         => '1',
        CLR        => '0',
        D          => sdatb_45_dly,
        PRE        => '0');