pkg_xilinx.vhd

使用ＩＤＥＬＡＹ实现８倍过采样异步串行信号恢复信号

    function GET_RLOC16_GRID ( inp : integer; orig_x : integer := 0; orig_y : integer := 0 )    return string;

    function Get_RLOC16_PACK1 ( inp : integer; orig_x : integer := 0; orig_y : integer := 0 )   return string;
    function Get_RLOC8_PACK1  ( inp : integer; orig_x : integer := 0; orig_y : integer := 0 )   return string;

    --------------------------------------------------
    --      constantS
    --------------------------------------------------

    -- Zero vectors
    constant ZERO_7 : std_logic_vector(6 downto 0) := "0000000";
    constant ZERO_8 : std_logic_vector( 7 downto 0 ) := "00000000";
    constant ZERO_13 : std_logic_vector( 12 downto 0 ) := "0000000000000";
    constant ZERO_14 : std_logic_vector(13 downto 0) := "00" & x"000";
    constant ZERO_16 : std_logic_vector( 15 downto 0 ) := "0000000000000000";
    constant ZERO_18 : std_logic_vector( 17 downto 0 ) := "000000000000000000";
    constant ZERO_32 : std_logic_vector(31 downto 0) := x"00000000";

    constant UZERO_13 : unsigned( 12 downto 0 ) := to_unsigned(0,13);
    constant SZERO_16 : signed(15 downto 0) := to_signed(0, 16);

    -- Control Signals
    constant SNUM       : integer := 0;
    constant UNUM       : integer := 1;
    constant ADD        : std_logic := '1';
    constant SUBSTRACT  : std_logic := '0';
    constant ENABLE     : std_logic := '1';
    constant logic0     : std_logic := '0';
    constant logic1     : std_logic := '1';

end PKG_XILINX;

---------------------------------------------------------------------------
-- Package Body
---------------------------------------------------------------------------

package body PKG_XILINX is

    --  int_to_lv
    --
    --  Convert an integer into a std_logic_vector
    function int_to_lv (inp, width, arith : integer)
    return std_logic_vector is
        variable result : std_logic_vector(width-1 downto 0);
        variable unsigned_val : unsigned(width-1 downto 0);
        variable signed_val : signed(width-1 downto 0);
    begin
        if (arith = SNUM) then
            signed_val := to_signed(inp, width);
            result := std_logic_vector(signed_val);
        else
            unsigned_val := to_unsigned(inp, width);
            result := std_logic_vector(unsigned_val);
        end if;
        return result;
    end;

    --  lv_to_int
    --
    --  Convert an std_logic or std_logic_vector to an integer
    function lv_to_int (inp : std_logic_vector; arith : integer)
    return integer is
        constant width : integer := inp'length;
        variable unsigned_val : unsigned(width-1 downto 0);
        variable signed_val : signed(width-1 downto 0);
        variable result : integer;
    begin
        if (arith = SNUM) then
            signed_val := signed(inp);
            result := to_integer(signed_val);
        else
            unsigned_val := unsigned(inp);
            result := to_integer(unsigned_val);
        end if;
        return result;
    end;

    --  Convert a real value to an unsigned vector
    --      e.g real_to_usigned(3.25, 3, 2) = 011_01
    --
    function real_to_un( r : real; INT_W : integer; DEC_W : integer )
    return unsigned is
        variable unit       : real;
        variable int        : integer;
        variable dec        : real;
        variable dec_int    : integer;
        variable un         : unsigned(INT_W+DEC_W-1 downto 0);
    begin
        unit    := 1.0 / 2.0**DEC_W;  -- 1/2^DEC_W
        int     := integer(r);
        dec     := r - real(int);
        dec_int := integer(dec / unit);

        un := to_unsigned(int, INT_W) & to_unsigned(dec_int, DEC_W);

        return un;
    end;

    --  max
    --
    function max(L, R: INTEGER) return INTEGER is
    begin
        if L > R then
            return L;
        else
            return R;
        end if;
    end;

    --  min
    --
    function min(L, R: INTEGER) return INTEGER is
    begin
        if L < R then
            return L;
        else
            return R;
        end if;
    end;

    --  max_lv
    --
    function max_lv(L, R: std_logic_vector)
    return std_logic_vector is
        constant wL : integer := L'length;
        constant wR : integer := L'length;
        variable width : integer;
        variable Lint : integer;
        variable Rint : integer;
        variable maxval : integer;
    begin
        Lint := lv_to_int(L, SNUM);
        Rint := lv_to_int(R, SNUM);
        maxval := max(Lint,Rint);
        width := max(wL,wR);
        return int_to_lv(maxval, width, SNUM);
    end;

    --  min_lv
    --
    function min_lv(L, R: std_logic_vector)
    return std_logic_vector is
        constant wL : integer := L'length;
        constant wR : integer := L'length;
        variable width : integer;
        variable Lint : integer;
        variable Rint : integer;
        variable minval : integer;
    begin
        Lint := lv_to_int(L, SNUM);
        Rint := lv_to_int(R, SNUM);
        minval := min(Lint,Rint);
        width := min(wL,wR);
        return int_to_lv(minval, width, SNUM);
    end;

    --
    --  operator +      LHS must have more bits than RHS.  Unsigned add.
    --
    function "+" (L : std_logic_vector; R : std_logic_vector)
    return std_logic_vector is
        constant wL : integer := L'length;
        constant wR : integer := R'length;
        variable Lun : unsigned(wL-1 downto 0);
        variable Run : unsigned(wL-1 downto 0);
        variable sum : unsigned(wL-1 downto 0);
    begin
        if wL < wR then
            ASSERT false
            REPORT "PKG_XILINX (251): left hand side must contain more bits than right hand side."
            SEVERITY error;
        end if;

        Lun := unsigned(L);

        if wR = wL then
            Run := unsigned(R);
        elsif wR < wL then
            Run(wR-1 downto 0) := unsigned(R);
            Run(wL-1 downto wR) := (others => '0');
        else
            Run := (others => 'X');
        end if;

        sum := Lun + Run;

        return std_logic_vector(sum);
    end;

    function "+" (L : std_logic_vector; R : integer)
    return std_logic_vector is
        constant wL : integer := L'length;
        variable Lun : unsigned(wL-1 downto 0);
        variable sum : unsigned(wL-1 downto 0);
    begin
        Lun := unsigned(L);
        sum := Lun + to_unsigned(R,wL);
        return std_logic_vector(sum);
    end;

    --  operator -
    --
    function "-" (L : std_logic_vector; R : integer)
    return std_logic_vector is
        constant wL : integer := L'length;
        variable Lun : unsigned(wL-1 downto 0);
        variable sum : unsigned(wL-1 downto 0);
    begin
        Lun := unsigned(L);
        sum := Lun - to_unsigned(R,wL);
        return std_logic_vector(sum);
    end;

    --  operator =
    --
    function "=" (L : std_logic_vector; R : integer)
    return boolean is
        constant wL : integer := L'length;
        variable Lint : integer;
        variable result : boolean;
    begin
        Lint := lv_to_int(L, UNUM);
        if Lint = R then
            result := true;
        else
            result := false;
        end if;
        return result;
    end;

    --  Wrap around unsigned adder
    --
    function add_wrap( inpA, inpB, ceiling : integer ) return integer is
        variable result : integer;
    begin
        if inpA + inpB <= ceiling then
            result := inpA + inpB;
        else
            result := inpA + inpB - (ceiling+1);
        end if;

        return result;
    end;

    --  Wrap around unsigned adder
    --
    function add_wrap( inpA : std_logic_vector; inpB, ceiling : integer ) return std_logic_vector is
        constant W_A    : integer := inpA'length;

        variable inpA_i : integer;
        variable r_i    : integer;
        variable result : std_logic_vector(W_A-1 downto 0);
    begin
        inpA_i  := lv_to_int( inpA, UNUM );
        r_i     := add_wrap( inpA_i, inpB, ceiling );
        result  := int_to_lv( r_i, W_A, UNUM );
        return result;
    end;