par_descrambler.vhd

使用ＩＤＥＬＡＹ实现８倍过采样异步串行信号恢复信号

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-- Copyright (c) 2004 Xilinx, Inc. 
-- All Rights Reserved 
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--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /   Vendor: Xilinx 
-- \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
--  \   \        Filename: $RCSfile: par_descrambler.vhd,rcs $
--  /   /        Date Last Modified:  $Date: 2004-08-27 10:05:14-06 $
-- /___/   /\    Date Created: August 14, 2001 
-- \   \  /  \ 
--  \___\/\___\ 
-- 
--
-- Revision History: 
-- $Log: par_descrambler.vhd,rcs $
-- Revision 1.0  2004-08-27 10:05:14-06  jsnow
-- Initial release.
--
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--   
--   XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" 
--   AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND 
--   SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, 
--   OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, 
--   APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION 
--   THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, 
--   AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE 
--   FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY 
--   WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE 
--   IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR 
--   REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF 
--   INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
--   FOR A PARTICULAR PURPOSE. 
--
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--
-- Description of module:
-- 
-- SMPTE 259M-1997 serial digital interface (SDI) is a standard for transmitting
-- digital video over a serial link.
-- 
-- SDI specifies that the serial bit stream shall be encoded in two ways. First,
-- a generator polynomial of x^9 + x^4 + 1 is used to generate a scrambled NRZ 
-- bit sequence. Next, a generator polynomial of x + 1 is used to produce the 
-- final polarity free NRZI sequence which is transmitted over the physical 
-- layer.
-- 
-- The descrambler module described in this file sits at the receiving end of 
-- the serial digital interface link and reverses the two encoding steps to 
-- extract the original data. First, the x + 1 generator polynomial is used to 
-- convert the bit stream from NRZI to NRZ. Next, the x^9 + x^4 + 1 generator 
-- polynomial is used to descramble the data.
-- 
-- This module works in parallel on 10-bits at a time. The module treats the 
-- data as a serial bit stream and isn't concerned about where the actual 
-- character boundaries are in the bit stream. A parallel implementation, like 
-- this one, consumes more logic than a serial implementation, but only has to 
-- run at one tenth the clock frequency of a serial implementation.
-- 
-- This module has a ld input which acts as a clock enable to all the registers
-- in the descrambler. If desired, this allows the input clock to run at the 
-- serial bit rate if the ld signal is asserted once every 10 clock cycles.
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity par_descrambler is
    port (
        clk:    in  std_ulogic;                     -- input clock
        rst:    in  std_ulogic;                     -- reset signal
        ld:     in  std_ulogic;                     -- load enable
        d:      in  std_ulogic_vector(9 downto 0);  -- input data bus
        q:      out std_ulogic_vector(9 downto 0)   -- output data bus
    );
end par_descrambler;

architecture synth of par_descrambler is

-- Internal signals 
signal prev_d9:     std_ulogic;                     -- previous d[9] bit
signal desc_in_reg: std_ulogic_vector(8 downto 0);  -- input reg of the descrambler
signal desc_wide:   std_ulogic_vector(18 downto 0); -- concat of two input words
signal nrz:         std_ulogic_vector(9 downto 0);  -- output of NRZ-to-NRZI

begin
    
    --
    -- prev_d9 register
    --
    -- This register holds the MSB of the previous clock period's d input so 
    -- that an eleven bit input vector is available to the NRZI-to-NRZ converter.
    -- 
    process(clk, rst, ld)
    begin
        if (rst = '1') then
            prev_d9 <= '0';
        elsif (clk'event and clk = '1') then
            if (ld = '1') then
                prev_d9 <= d(9);
            end if;
        end if; 
    end process;

    --
    -- NRZI-to-NRZ converter
    --
    -- The 10 XOR gates generated by this statement convert the 11-bit wide
    -- nrzi data to 10 bits of NRZ data. Each bit from the d input ix XORed with
    -- the bit that preceeded it in the bit stream. The LSB of d is XORed with 
    -- the  MSB of d from the previous clock period that is held in the prev_d9 
    -- register.
    --
    nrz <= d xor (d(8 downto 0) & prev_d9);

    --
    -- desc_in_reg: Input register of the SDI descrambler
    --
    -- This register is a pipeline delay register which loads from the output of
    -- the NRZI-to-NRZ converter. It only holds the nine MSBs from the converter
    -- that get combined with 10-bits coming from the converter on the next 
    -- clock cylce to form a 19-bit wide input vector to the descrambler.
    --
    process(clk, rst, ld)
    begin
        if (rst = '1') then
            desc_in_reg <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ld = '1') then
                desc_in_reg <= nrz(9 downto 1);
            end if;
        end if; 
    end process;

    desc_wide <= nrz & desc_in_reg;

    -- 
    -- Descrambler
    --
    -- A for loop is used to generate the SDI x^9 + x^4 + 1 polynomial for 
    -- each of the 10-bits to be output using the 19-bit desc_wide input vector 
    -- that is made up of the contents of the desc_in_reg and the output of the
    -- NRZI-to-NRZ converter.
    --
    process(clk, rst, ld)
    begin
        if (rst = '1') then
            q <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ld = '1') then
                for i in 0 to 9 loop
                    q(i) <= desc_wide(i) xor desc_wide(i + 4) 
                            xor desc_wide(i + 9);
                end loop;
            end if;
        end if;
    end process;        

end synth;