📄 example_sdsdi_lvds_top.v
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//------------------------------------------------------------------------------
// Copyright (c) 2006 Xilinx, Inc.
// All Rights Reserved
//------------------------------------------------------------------------------
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
// \ \ Filename: $RCSfile: example_sdsdi_lvds_top.v,rcs $
// / / Date Last Modified: $Date: 2006-09-22 14:00:03-06 $
// /___/ /\ Date Created: July 17, 2006
// \ \ / \
// \___\/\___\
//
//
// Revision History:
// $Log: example_sdsdi_lvds_top.v,rcs $
// Revision 1.0 2006-09-22 14:00:03-06 jsnow
// Initial release.
//
//------------------------------------------------------------------------------
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
// SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
// XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
// AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
// OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
// IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
// AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
// FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
// WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
// IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
// INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE.
//
//------------------------------------------------------------------------------
/*
Description of module:
This is an example of using the IDELAY-based 8X oversampler to receive two
SD-SDI bitstreams at 270 Mbps.
--------------------------------------------------------------------------------
*/
module example_sdsdi_lvds_top
(
// Clock sources and clock source control signals
input wire PAD_clk_200M_p, // 200 MHz Clock for IDELAY reference
input wire PAD_clk_200M_n,
input wire PAD_clk_270M_p, // 270 MHz LVDS clock source
input wire PAD_clk_270M_n,
// SDI Interface Data and Control Signals
input wire PAD_sdsdi1_rxp, // SD-SDI serial input LVDS pair #1
input wire PAD_sdsdi1_rxn,
input wire PAD_sdsdi2_rxp, // SD-SDI serial input LVDS pair #2
input wire PAD_sdsdi2_rxn,
// Output Signals
output wire PAD_clkout_p, // 270 MHz clock output
output wire PAD_clkout_n,
output wire PAD_rx1_ce, // Rx #1 clock enable
output wire [9:0] PAD_rx1_video, // Rx #1 video data
output wire PAD_rx2_ce, // Rx #2 clock enable
output wire [9:0] PAD_rx2_video // Rx #2 video data
);
//-----------------------------------------------------------------------------
// Signal definitions
//
// Clock signals
wire clk_270M_in; // 270 MHz clock before DCM
wire dcm270_clk0; // clk0 output of DCM270
wire dcm270_clk90; // clk90 output of DCM270
wire gclk_270M; // global 270 MHz clock
wire gclk_270M_90; // global 270 MHz clock shifted 90 degrees
wire gclk_200M; // global 200 MHz clock
wire clk_200M_in; // 200 MHz clock input
wire idly_rdy; // RDY output of IDELAYCTRL primitive
// Signals for SD-SDI Rx #1
wire rx1_ce;
wire [19:0] rx1_ovrs_dout;
wire rx1_ovrs_rdy;
wire [9:0] rx1_recdata;
wire [9:0] rx1_dscout;
wire [9:0] rx1_video;
// Signals for SD-SDI Rx #2
wire rx2_ce;
wire [19:0] rx2_ovrs_dout;
wire rx2_ovrs_rdy;
wire [9:0] rx2_recdata;
wire [9:0] rx2_dscout;
wire [9:0] rx2_video;
//------------------------------------------------------------------------------
// Clock input buffers and global clock buffers
//
IBUFGDS # (
.IOSTANDARD ("LVDS_25"),
.DIFF_TERM ("TRUE"))
IBUFCLK200 (
.I (PAD_clk_200M_p),
.IB (PAD_clk_200M_n),
.O (clk_200M_in));
BUFG BUFG200M (
.I (clk_200M_in),
.O (gclk_200M));
//
// IDELAYCTRL
//
IDELAYCTRL DLYCTRL (
.REFCLK (gclk_200M),
.RDY (idly_rdy),
.RST (1'b0));
//
// 270 MHz clock input, DCM, and global clock buffers
//
// This DCM produces 0 degree and 90 degree phases of the 270 MHz input clock.
//
IBUFGDS #(
.IOSTANDARD ("LVDS_25"),
.DIFF_TERM ("TRUE"))
IBUFCLK270 (
.I (PAD_clk_270M_p),
.IB (PAD_clk_270M_n),
.O (clk_270M_in));
DCM_ADV #(
.CLK_FEEDBACK ("1X"),
.CLKDV_DIVIDE (2.000000),
.CLKFX_DIVIDE (1),
.CLKFX_MULTIPLY (4),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (3.7037),
.CLKOUT_PHASE_SHIFT ("NONE"),
.DCM_AUTOCALIBRATION ("TRUE"),
.DCM_PERFORMANCE_MODE ("MAX_SPEED"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.DFS_FREQUENCY_MODE ("LOW"),
.DLL_FREQUENCY_MODE ("HIGH"),
.DUTY_CYCLE_CORRECTION ("TRUE"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"),
.FACTORY_JF (16'hF0F0))
DCM270 (
.CLKFB (gclk_270M),
.CLKIN (clk_270M_in),
.DADDR (7'b0000000),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0000),
.DWE (1'b0),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.RST (1'b0),
.CLKDV (),
.CLKFX (),
.CLKFX180 (),
.CLK0 (dcm270_clk0),
.CLK2X (),
.CLK2X180 (),
.CLK90 (dcm270_clk90),
.CLK180 (),
.CLK270 (),
.DO (),
.DRDY (),
.LOCKED (),
.PSDONE ());
BUFG BUFG270M (
.I (dcm270_clk0),
.O (gclk_270M));
BUFG BUFG270M90 (
.I (dcm270_clk90),
.O (gclk_270M_90));
//------------------------------------------------------------------------------
//
// SD-SDI Rx #1
//
//
// 8X oversampler
//
(* RLOC = "X0Y0" *)
oversample_8x #(
.IDELAY_45_DEGREES (6))
OVRSAMPLE1 (
.clk0 (gclk_270M),
.clk90 (gclk_270M_90),
.PAD_din_p (PAD_sdsdi1_rxp),
.PAD_din_n (PAD_sdsdi1_rxn),
.dout_rdy (rx1_ovrs_rdy),
.dout (rx1_ovrs_dout));
//
// DRU
//
// The DRU is dual ported, handling both SD-SDI channels.
//
os48_1011x20bTo10b_top2 DRU (
.rst (1'b0),
.bitOrderDinLSB (1'b1), // LSB first input
.bitOrderDoutLSB (1'b1), // LSB first on output
.A_recclk (gclk_270M),
.A_en (rx1_ovrs_rdy),
.A_mode (2'b01), // 8X oversampling
.A_din20b (rx1_ovrs_dout),
.A_dout10bEn (rx1_ce),
.A_dout10b (rx1_recdata),
.A_dout20bEn (),
.A_dout20b (),
.B_recclk (gclk_270M),
.B_en (rx2_ovrs_rdy),
.B_mode (2'b01),
.B_din20b (rx2_ovrs_dout),
.B_dout10bEn (rx2_ce),
.B_dout10b (rx2_recdata),
.B_dout20bEn (),
.B_dout20b ());
//
// Put KEEP attributes on the two clock enables from the DRU so that their
// names are preserved and they can be referenced in the UCF file to develop
// the multi-cycle timing constraints.
//
// synthesis attribute keep of rx1_ce is "TRUE";
// synthesis attribute keep of rx2_ce is "TRUE";
//
// SD-SDI decoder
//
par_descrambler DSC1 (
.clk (gclk_270M),
.rst (1'b0),
.ld (rx1_ce),
.d (rx1_recdata),
.q (rx1_dscout));
//
// SD-SDI framer
//
par_framer FRM1 (
.clk (gclk_270M),
.rst (1'b0),
.ce (rx1_ce),
.d (rx1_dscout),
.frame_en (1'b1),
.q (rx1_video),
.trs (),
.nsp ());
assign PAD_rx1_video = rx1_video;
assign PAD_rx1_ce = rx1_ce;
//------------------------------------------------------------------------------
//
// SD-SDI Rx #2
//
//
// 8X oversampler
//
(* RLOC = "X0Y0" *)
oversample_8x #(
.IDELAY_45_DEGREES (6))
OVRSAMPLE2 (
.clk0 (gclk_270M),
.clk90 (gclk_270M_90),
.PAD_din_p (PAD_sdsdi2_rxp),
.PAD_din_n (PAD_sdsdi2_rxn),
.dout_rdy (rx2_ovrs_rdy),
.dout (rx2_ovrs_dout));
//
// Data recovery is done by the dual ported DRU instantiated as part of Rx #1.
//
//
// SMPTE decoder
//
par_descrambler DSC2 (
.clk (gclk_270M),
.rst (1'b0),
.ld (rx2_ce),
.d (rx2_recdata),
.q (rx2_dscout));
//
// Framer
//
par_framer FRM2 (
.clk (gclk_270M),
.rst (1'b0),
.ce (rx2_ce),
.d (rx2_dscout),
.frame_en (1'b1),
.q (rx2_video),
.trs (),
.nsp ());
assign PAD_rx2_video = rx2_video;
assign PAD_rx2_ce = rx2_ce;
OBUFDS #(
.IOSTANDARD ("LVDS_25"))
OBUF270 (
.I (gclk_270M),
.O (PAD_clkout_p),
.OB (PAD_clkout_n));
endmodule
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