par_framer.v

使用ＩＤＥＬＡＹ实现８倍过采样异步串行信号恢复信号

//------------------------------------------------------------------------------ 
// Copyright (c) 2005 Xilinx, Inc. 
// All Rights Reserved 
//------------------------------------------------------------------------------ 
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /   Vendor: Xilinx 
// \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
//  \   \        Filename: $RCSfile: par_framer.v,rcs $
//  /   /        Date Last Modified:  $Date: 2005-01-18 11:08:05-07 $
// /___/   /\    Date Created: Jan 5, 2005 
// \   \  /  \ 
//  \___\/\___\ 
// 
//
// Revision History: 
// $Log: par_framer.v,rcs $
// Revision 1.1  2005-01-18 11:08:05-07  jsnow
// Header update.
//
//------------------------------------------------------------------------------ 
//
//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
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//     FOR A PARTICULAR PURPOSE.
//
//------------------------------------------------------------------------------ 
/*
Description of module:

SMPTE 259M-1997 serial digital interface (SDI) is a standard for transmitting
digital video over a serial link.

This module accepts 10-bit parallel "unframed" data words from the SDI
descrambler module and examines the bit stream for the 30-bit TRS pramble. Once
a TRS is found, the framer then knows the bit boundary of all subsequent 10-bit
characters in the bit stream and uses this offset to generate a 10-bit parallel
data word on its output.

The module has the following control inputs:

ce: The clock enable input controls loading of all registers in the module. It
must be asserted whenever a new 10-bit word is to be loaded into the module. By
providing a clock enable, this module can use a clock that is running at the
bit rate of the SDI bit stream if ce is asserted once every ten clock cycles.

frame_en: This input controls whether the framer rsynchronize to new character
offsets when out-of-phase TRS symbols are detected. When this input is high,
out-of-phase TRS symbols will cause the framer to resynchronize.

The module generates the following outputs:

q: This 10-bit output port contains the properly framed data word. The data is
normally valid on this port for 10 clock cycles.

trs: (timing reference signal) This output is asserted when the q output
register holds any of the four words of a TRS.

nsp: (new start position) If frame_en is low and a TRS is detected that does not
match the current character offset, this signal will be asserted high. The nsp
signal will remain asserted until the offset error has been corrected..

There are normally three ways to use the frame_en input:

frame_en tied high: When frame_en is tied high, the framer will resynchronize
on every TRS detected. 

frame_en tied to nsp: When in this mode, the framer implements TRS filtering.
If a TRS is detected that is out of phase with the existing character offset,
nsp will be asserted, but the framer will not resynchronize. If the next TRS
received is in phase with the current character offset, nsp will go low and the
will not resynchronize. If the next TRS arrives out of phase with the current
character offset, then the new character offset will be loaded and nsp will be
deasserted. Single erroneous TRS  are ignored in this mode, but if they persist,
the decoder will adjust.

frame_en tied low: The automatic framing function is disabled when frame_en is
tied low. If data is being sent across the interface that does not comply with
the SDI standard and may contain data that looks like TRS symbols, the framing
function can be disabled in this manner.
--------------------------------------------------------------------------------
*/

`timescale 1ns / 1ns

module par_framer (
    clk,                            // input clock
    rst,                            // reset signal
    ce,                             // clock enable
    d,                              // input data
    frame_en,                       // enables resynchronization when high
    q,                              // output data
    trs,                            // asserted when out reg contains a TRS character
    nsp                             // new start position detected
);

// IO definitions   
input               clk;
input               rst;
input               ce;
input   [9:0]       d;
input               frame_en;
output  [9:0]       q;
output              trs;
output              nsp;

// Internal registers
reg     [9:0]       in1_reg;        // input register 1 
reg     [9:0]       in2_reg;        // input register 2
reg     [9:0]       in3_reg;        // input register 3
reg     [3:0]       offset_reg;     // offset register
reg     [18:0]      barrel_in;      // input register for the barrel shifter
reg                 nsp;            // nsp output register
reg     [3:0]       trs_out;        // used to generate the trs output signal

// Internal signals
wire    [38:0]      in_vector;      // concatenation of the four input registers
reg     [9:0]       trs_match1;     // which offsets in in_vector[18:0] match 0x3ff
reg     [9:0]       trs_match2;     // which offsets in in_vector[28:10] match 0x000
reg     [9:0]       trs_match3;     // which offsets in in_vector[38:29] match 0x000
wire    [9:0]       trs_match_all;  // which offsets match complete 30-bit TRS symbol
reg     [15:0]      trs_match1_l1;  // intermediate level of gate outputs in TRS detector
reg     [15:0]      trs_match2_l1;  // intermediate level of gate outputs in TRS detector
reg     [15:0]      trs_match3_l1;  // intermediate level of gate outputs in TRS detector
wire                trs_detected;   // asserted when TRS symbol is detected
reg                 trs_error;      // more than one offset matched the TRS symbol
wire    [3:0]       offset_val;     // calculated offset value to load into offset_reg
reg     [9:0]       barrel_out;     // output of barrel shifter
wire                new_offset;     // mismatch between offset_val and offset_reg
wire    [20:0]      bs_in;          // barrel shifter input vector (2 MSBs are dummy)
reg     [12:0]      bs_m1;          // output of first MUX level in barrel shifter
wire    [1:0]       bs_sm;          // barrel shifter first level MUX select bits
wire    [1:0]       bs_sl;          // barrel shifter second level MUX select bits

integer             i, j;           // for loop variables

//
// Input registers 1, 2, and 3
//
// The following three registers form a 3-character deep pipeline
// which will be examined by the 39-bit wide TRS detector.
//
always @ (posedge clk or posedge rst)
    if (rst)
        begin
            in1_reg <= 0;
            in2_reg <= 0;
            in3_reg <= 0;
        end
    else if (ce)
        begin
            in1_reg <= d;
            in2_reg <= in1_reg;
            in3_reg <= in2_reg;
        end
    
//
// TRS detector and offset encoder
//
// The TRS detector finds 30-bit TRS preambles (0x3ff, 0x000, 0x000) in the
// input data stream. The TRS detector scans a 39-bit input vector
// consisting of all the bits from the three input registers plus the LS
// 9 bits of the d input data.
//
// The detector consists two main parts. 
//
// The first part is a series 10-bit AND and NOR gates that examine each
// possible bit location in the 39 input vector for the TRS preamble. These
// 10-bit wide AND and NOR gates have been coded here as two levels of
// 3 and 4 input gates because this results in a more compact implementation
// in most synthesis engines. 
//
// The outputs of these gates are assigned to the vectors trs_match1, 2, 
// and 3. These three vectors each contain 10 unary bits which indicate which 
// offset(s) matched the pattern being detected. ANDing these three vectors
// together generates another 10-bit vector called trs_match_all whose bits
// indicate which offset(s) matches the entire 30-bit TRS preamble.
//
// After the starting position of the TRS preamble has been detected, it must
// be encoded into an offset value which can drive the barrel shifter. The
// TRS encoder generates a 4-bit offset_val which contains the bit offset of
// the TRS preamble. It also generates a trs_error signal which is asserted if
// more than one start position is detected simulataneously.
// 
assign in_vector = {d[8:0], in1_reg, in2_reg, in3_reg};

// first level of gates

always @ (in_vector)
    begin
        trs_match1_l1[ 0] <=  &in_vector[ 3: 0];
        trs_match1_l1[ 1] <=  &in_vector[ 4: 1];
        trs_match1_l1[ 2] <=  &in_vector[ 5: 2];
        trs_match1_l1[ 3] <=  &in_vector[ 6: 3];
        trs_match1_l1[ 4] <=  &in_vector[ 7: 4];
        trs_match1_l1[ 5] <=  &in_vector[ 8: 5];
        trs_match1_l1[ 6] <=  &in_vector[ 9: 6];
        trs_match1_l1[ 7] <=  &in_vector[10: 7];
        trs_match1_l1[ 8] <=  &in_vector[11: 8];
        trs_match1_l1[ 9] <=  &in_vector[12: 9];
        trs_match1_l1[10] <=  &in_vector[13:10];
        trs_match1_l1[11] <=  &in_vector[14:11];
        trs_match1_l1[12] <=  &in_vector[15:12];
        trs_match1_l1[13] <=  &in_vector[16:13];
        trs_match1_l1[14] <=  &in_vector[17:14];
        trs_match1_l1[15] <=  &in_vector[18:15];

        trs_match2_l1[ 0] <= ~|in_vector[13:10];
        trs_match2_l1[ 1] <= ~|in_vector[14:11];
        trs_match2_l1[ 2] <= ~|in_vector[15:12];
        trs_match2_l1[ 3] <= ~|in_vector[16:13];
        trs_match2_l1[ 4] <= ~|in_vector[17:14];
        trs_match2_l1[ 5] <= ~|in_vector[18:15];
        trs_match2_l1[ 6] <= ~|in_vector[19:16];
        trs_match2_l1[ 7] <= ~|in_vector[20:17];
        trs_match2_l1[ 8] <= ~|in_vector[21:18];