par_descrambler.v

使用ＩＤＥＬＡＹ实现８倍过采样异步串行信号恢复信号

//------------------------------------------------------------------------------ 
// Copyright (c) 2004 Xilinx, Inc. 
// All Rights Reserved 
//------------------------------------------------------------------------------ 
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /   Vendor: Xilinx 
// \   \   \/    Author: John F. Snow, Advanced Product Division, Xilinx, Inc.
//  \   \        Filename: $RCSfile: par_descrambler.v,rcs $
//  /   /        Date Last Modified:  $Date: 2004-10-15 09:36:16-06 $
// /___/   /\    Date Created: October 15, 2004 
// \   \  /  \ 
//  \___\/\___\ 
// 
//
// Revision History: 
// $Log: par_descrambler.v,rcs $
// Revision 1.1  2004-10-15 09:36:16-06  jsnow
// Header update.
//
//------------------------------------------------------------------------------ 
//
//     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
//     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
//     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
//     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
//     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
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//     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
//     FOR A PARTICULAR PURPOSE.
//
//------------------------------------------------------------------------------ 
/*
Description of module:

SMPTE 259M-1997 serial digital interface (SDI) is a standard for transmitting
digital video over a serial link.

SDI specifies that the serial bit stream shall be encoded in two ways. First, a
generator polynomial of x^9 + x^4 + 1 is used to generate a scrambled NRZ bit
sequence. Next, a generator polynomial of x + 1 is used to produce the final
polarity free NRZI sequence which is transmitted over the physical layer.

The descrambler module described in this file sits at the receiving end of the
serial digital interface link and reverses the two encoding steps to extract the
original data. First, the x + 1 generator polynomial is used to convert the bit
stream from NRZI to NRZ. Next, the x^9 + x^4 + 1 generator polynomial is used
to descramble the data.

This module works in parallel on 10-bits at a time. The module treats the data
as a serial bit stream and isn't concerned about where the actual character
boundaries are in the bit stream. A parallel implementation, like this one,
consumes more logic than a serial implementation, but only has to run at one
tenth the clock frequency of a serial implementation.

This module has a ld input which acts as a clock enable to all the  registers
in the descrambler. If desired, this allows the input clock to run at the serial
bit rate if the ld signal is asserted once every 10 clock cycles.
--------------------------------------------------------------------------------
*/

`timescale 1ns / 1ns

module par_descrambler (
    clk,                            // input clock
    rst,                            // reset signal
    ld,                             // load enable
    d,                              // input data
    q                               // output data
);

// IO definitions   
input               clk;
input               rst;
input               ld;
input   [9:0]       d;
output  [9:0]       q;

// Internal registers 
reg                 prev_d9;        // previous d[9] bit register
reg     [8:0]       desc_in_reg;    // input register of the SDI descrambler
reg     [9:0]       q;              // descrambled outputs

// Internal wires
wire    [18:0]      desc_wide;      // concat of two input words used by descrambler
wire    [9:0]       nrz;            // output of the NRZI-to-NRZ converter

integer             i;              // for loop variable
    
//
// prev_d9 register
//
// This register holds the MSB of the previous clock period's d input so that
// an eleven bit input vector is available to the NRZI-to-NRZ converter.
// 
always @ (posedge clk or posedge rst)
    if (rst)
        prev_d9 <= 0;
    else if (ld)
        prev_d9 <= d[9];


//
// NRZI-to-NRZ converter
//
// The 10 XOR gates generated by this statement convert the 11-bit wide
// nrzi data to 10 bits of NRZ data. Each bit from the d input ix XORed with
// the bit that preceeded it in the bit stream. The LSB of d is XORed with the 
// MSB of d from the previous clock period that is held in the prev_d9 register.
//
assign nrz = d ^ {d[8:0], prev_d9};

//
// desc_in_reg: Input register of the SDI descrambler
//
// This register is a pipeline delay register which loads from the output of the
// NRZI-to-NRZ converter. It only holds the nine MSBs from the converter which
// get combined with 10-bits coming from the converter on the next clock cylce
// to form a 19-bit wide input vector to the descrambler.
//
always @ (posedge clk or posedge rst)
    if (rst)
        desc_in_reg <= 0;
    else if (ld)
        desc_in_reg <= nrz[9:1];

assign desc_wide = {nrz, desc_in_reg};

// 
// Descrambler
//
// A for loop is used to generate the SDI x^9 + x^4 + 1 polynomial for 
// each of the 10-bits to be output using the 19-bit desc_wide input vector 
// that is made up of the contents of the desc_in_reg and the output of the
// NRZI-to-NRZ converter.
//
always @ (posedge clk or posedge rst)
    if (rst)
        q <= 0;
    else if (ld)
        for (i = 0; i < 10; i = i + 1)
            q[i] <= desc_wide[i] ^ desc_wide[i + 4] ^ desc_wide[i + 9];
        
endmodule