readme.txt

使用ＩＤＥＬＡＹ实现８倍过采样异步串行信号恢复信号

XAPP861 version 1.0 reference design files:

Verilog Directory:
    example_sdsdi_lvds_top.v		Top level example reference desing
	example_sdsdi_lvds_top.ucf		Constraint file for top level example
	oversample_8x.v					8X oversampler module
	par_descrambler.v				SMPTE 259M SD-SDI descrambler
	par_framer.v					SMPTE 259M SD-SDI framer

VHDL Directory:
    example_sdsdi_lvds_top.vhd		Top level example reference desing
	example_sdsdi_lvds_top.ucf		Constraint file for top level example
	oversample_8x.vhd				8X oversampler module
	par_descrambler.vhd				SMPTE 259M SD-SDI descrambler
	par_framer.vhd					SMPTE 259M SD-SDI framer
	ff_fifo2e.vhd					DRU file
	ff_fifo2e_10b.vhd				DRU file
	os48_1011x20bTo10b.vhd			DRU file
	os48_1011x20bTo10b_top2.vhd		Top level of DRU
	osDeci20b_48_1011x_BRAM.vhd		DRU file
	sipoCtl10b_BRAM_v2.vhd			DRU SIPO control for Virtex-4
	sipoCtl10b_BRAM_v2_virtex5.vhd	DRU SIPO control for Virtex-5
	PKG_OVERSAMP.vhd				Package file for DRU
	PKG_XILINX.vhd					Package file for DRU
	
Revision History
----------------
Release 1.0: 2006/09/22:

Initial release of IDELAY-based 8X oversampler. 

The oversample_8x module and the top level example files are available in 
both Verilog and VHDL. However, the DRU is only available in VHDL. Use mixed 
language simulation and synthesis to include this DRU in a Verilog design.