📄 io_map.h
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#define SPIBR_SPR2 _SPIBR.Bits.SPR2
#define SPIBR_SPPR0 _SPIBR.Bits.SPPR0
#define SPIBR_SPPR1 _SPIBR.Bits.SPPR1
#define SPIBR_SPPR2 _SPIBR.Bits.SPPR2
#define SPIBR_SPR _SPIBR.MergedBits.grpSPR
#define SPIBR_SPPR _SPIBR.MergedBits.grpSPPR
#define SPIBR_SPR0_MASK 0x01
#define SPIBR_SPR1_MASK 0x02
#define SPIBR_SPR2_MASK 0x04
#define SPIBR_SPPR0_MASK 0x10
#define SPIBR_SPPR1_MASK 0x20
#define SPIBR_SPPR2_MASK 0x40
#define SPIBR_SPR_MASK 0x07
#define SPIBR_SPR_BITNUM 0x00
#define SPIBR_SPPR_MASK 0x70
#define SPIBR_SPPR_BITNUM 0x04
/*** SPIS - SPI Status Register; 0x0000002B ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte :1;
byte :1;
byte MODF :1; /* Master Mode Fault Flag */
byte SPTEF :1; /* SPI Transmit Buffer Empty Flag */
byte :1;
byte SPRF :1; /* SPI Read Buffer Full Flag */
} Bits;
} SPISSTR;
extern volatile SPISSTR _SPIS @0x0000002B;
#define SPIS _SPIS.Byte
#define SPIS_MODF _SPIS.Bits.MODF
#define SPIS_SPTEF _SPIS.Bits.SPTEF
#define SPIS_SPRF _SPIS.Bits.SPRF
#define SPIS_MODF_MASK 0x10
#define SPIS_SPTEF_MASK 0x20
#define SPIS_SPRF_MASK 0x80
/*** SPID - SPI Data Register; 0x0000002D ***/
typedef union {
byte Byte;
} SPIDSTR;
extern volatile SPIDSTR _SPID @0x0000002D;
#define SPID _SPID.Byte
/*** IICA - IIC Address Register; 0x00000030 ***/
typedef union {
byte Byte;
struct {
byte :1;
byte ADDR1 :1; /* IIC Address Bit 1 */
byte ADDR2 :1; /* IIC Address Bit 2 */
byte ADDR3 :1; /* IIC Address Bit 3 */
byte ADDR4 :1; /* IIC Address Bit 4 */
byte ADDR5 :1; /* IIC Address Bit 5 */
byte ADDR6 :1; /* IIC Address Bit 6 */
byte ADDR7 :1; /* IIC Address Bit 7 */
} Bits;
struct {
byte :1;
byte grpADDR_1 :7;
} MergedBits;
} IICASTR;
extern volatile IICASTR _IICA @0x00000030;
#define IICA _IICA.Byte
#define IICA_ADDR1 _IICA.Bits.ADDR1
#define IICA_ADDR2 _IICA.Bits.ADDR2
#define IICA_ADDR3 _IICA.Bits.ADDR3
#define IICA_ADDR4 _IICA.Bits.ADDR4
#define IICA_ADDR5 _IICA.Bits.ADDR5
#define IICA_ADDR6 _IICA.Bits.ADDR6
#define IICA_ADDR7 _IICA.Bits.ADDR7
#define IICA_ADDR_1 _IICA.MergedBits.grpADDR_1
#define IICA_ADDR IICA_ADDR_1
#define IICA_ADDR1_MASK 0x02
#define IICA_ADDR2_MASK 0x04
#define IICA_ADDR3_MASK 0x08
#define IICA_ADDR4_MASK 0x10
#define IICA_ADDR5_MASK 0x20
#define IICA_ADDR6_MASK 0x40
#define IICA_ADDR7_MASK 0x80
#define IICA_ADDR_1_MASK 0xFE
#define IICA_ADDR_1_BITNUM 0x01
/*** IICF - IIC Frequency Divider Register; 0x00000031 ***/
typedef union {
byte Byte;
struct {
byte ICR0 :1; /* IIC Clock Rate Bit 0 */
byte ICR1 :1; /* IIC Clock Rate Bit 1 */
byte ICR2 :1; /* IIC Clock Rate Bit 2 */
byte ICR3 :1; /* IIC Clock Rate Bit 3 */
byte ICR4 :1; /* IIC Clock Rate Bit 4 */
byte ICR5 :1; /* IIC Clock Rate Bit 5 */
byte MULT0 :1; /* Multiplier Factor Bit 0 */
byte MULT1 :1; /* Multiplier Factor Bit 1 */
} Bits;
struct {
byte grpICR :6;
byte grpMULT :2;
} MergedBits;
} IICFSTR;
extern volatile IICFSTR _IICF @0x00000031;
#define IICF _IICF.Byte
#define IICF_ICR0 _IICF.Bits.ICR0
#define IICF_ICR1 _IICF.Bits.ICR1
#define IICF_ICR2 _IICF.Bits.ICR2
#define IICF_ICR3 _IICF.Bits.ICR3
#define IICF_ICR4 _IICF.Bits.ICR4
#define IICF_ICR5 _IICF.Bits.ICR5
#define IICF_MULT0 _IICF.Bits.MULT0
#define IICF_MULT1 _IICF.Bits.MULT1
#define IICF_ICR _IICF.MergedBits.grpICR
#define IICF_MULT _IICF.MergedBits.grpMULT
#define IICF_ICR0_MASK 0x01
#define IICF_ICR1_MASK 0x02
#define IICF_ICR2_MASK 0x04
#define IICF_ICR3_MASK 0x08
#define IICF_ICR4_MASK 0x10
#define IICF_ICR5_MASK 0x20
#define IICF_MULT0_MASK 0x40
#define IICF_MULT1_MASK 0x80
#define IICF_ICR_MASK 0x3F
#define IICF_ICR_BITNUM 0x00
#define IICF_MULT_MASK 0xC0
#define IICF_MULT_BITNUM 0x06
/*** IICC - IIC Control Register; 0x00000032 ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte RSTA :1; /* Repeat START Bit */
byte TXAK :1; /* Transmit Acknowledge Enable Bit */
byte TX :1; /* Transmit Mode Select Bit */
byte MST :1; /* Master Mode Select Bit */
byte IICIE :1; /* IIC Interrupt Enable Bit */
byte IICEN :1; /* IIC Enable Bit */
} Bits;
} IICCSTR;
extern volatile IICCSTR _IICC @0x00000032;
#define IICC _IICC.Byte
#define IICC_RSTA _IICC.Bits.RSTA
#define IICC_TXAK _IICC.Bits.TXAK
#define IICC_TX _IICC.Bits.TX
#define IICC_MST _IICC.Bits.MST
#define IICC_IICIE _IICC.Bits.IICIE
#define IICC_IICEN _IICC.Bits.IICEN
#define IICC_RSTA_MASK 0x04
#define IICC_TXAK_MASK 0x08
#define IICC_TX_MASK 0x10
#define IICC_MST_MASK 0x20
#define IICC_IICIE_MASK 0x40
#define IICC_IICEN_MASK 0x80
/*** IICS - IIC Status Register; 0x00000033 ***/
typedef union {
byte Byte;
struct {
byte RXAK :1; /* Receive Acknowledge */
byte IICIF :1; /* IIC Interrupt Flag */
byte SRW :1; /* Slave Read/Write */
byte :1;
byte ARBL :1; /* Arbitration Lost */
byte BUSY :1; /* Bus Busy bit */
byte IAAS :1; /* Addressed as a Slave Bit */
byte TCF :1; /* Transfer Complete Flag */
} Bits;
} IICSSTR;
extern volatile IICSSTR _IICS @0x00000033;
#define IICS _IICS.Byte
#define IICS_RXAK _IICS.Bits.RXAK
#define IICS_IICIF _IICS.Bits.IICIF
#define IICS_SRW _IICS.Bits.SRW
#define IICS_ARBL _IICS.Bits.ARBL
#define IICS_BUSY _IICS.Bits.BUSY
#define IICS_IAAS _IICS.Bits.IAAS
#define IICS_TCF _IICS.Bits.TCF
#define IICS_RXAK_MASK 0x01
#define IICS_IICIF_MASK 0x02
#define IICS_SRW_MASK 0x04
#define IICS_ARBL_MASK 0x10
#define IICS_BUSY_MASK 0x20
#define IICS_IAAS_MASK 0x40
#define IICS_TCF_MASK 0x80
/*** IICD - IIC Data I/O Register; 0x00000034 ***/
typedef union {
byte Byte;
struct {
byte DATA0 :1; /* IIC Data Bit 0 */
byte DATA1 :1; /* IIC Data Bit 1 */
byte DATA2 :1; /* IIC Data Bit 2 */
byte DATA3 :1; /* IIC Data Bit 3 */
byte DATA4 :1; /* IIC Data Bit 4 */
byte DATA5 :1; /* IIC Data Bit 5 */
byte DATA6 :1; /* IIC Data Bit 6 */
byte DATA7 :1; /* IIC Data Bit 7 */
} Bits;
} IICDSTR;
extern volatile IICDSTR _IICD @0x00000034;
#define IICD _IICD.Byte
#define IICD_DATA0 _IICD.Bits.DATA0
#define IICD_DATA1 _IICD.Bits.DATA1
#define IICD_DATA2 _IICD.Bits.DATA2
#define IICD_DATA3 _IICD.Bits.DATA3
#define IICD_DATA4 _IICD.Bits.DATA4
#define IICD_DATA5 _IICD.Bits.DATA5
#define IICD_DATA6 _IICD.Bits.DATA6
#define IICD_DATA7 _IICD.Bits.DATA7
#define IICD_DATA0_MASK 0x01
#define IICD_DATA1_MASK 0x02
#define IICD_DATA2_MASK 0x04
#define IICD_DATA3_MASK 0x08
#define IICD_DATA4_MASK 0x10
#define IICD_DATA5_MASK 0x20
#define IICD_DATA6_MASK 0x40
#define IICD_DATA7_MASK 0x80
/*** ICSC1 - ICS Control Register 1; 0x00000038 ***/
typedef union {
byte Byte;
struct {
byte IREFSTEN :1; /* Internal Reference Stop Enable */
byte IRCLKEN :1; /* Internal Reference Clock Enable */
byte IREFS :1; /* Internal Reference Select */
byte RDIV0 :1; /* Reference Divider, bit 0 */
byte RDIV1 :1; /* Reference Divider, bit 1 */
byte RDIV2 :1; /* Reference Divider, bit 2 */
byte CLKS0 :1; /* Clock Source Select, bit 0 */
byte CLKS1 :1; /* Clock Source Select, bit 1 */
} Bits;
struct {
byte :1;
byte :1;
byte :1;
byte grpRDIV :3;
byte grpCLKS :2;
} MergedBits;
} ICSC1STR;
extern volatile ICSC1STR _ICSC1 @0x00000038;
#define ICSC1 _ICSC1.Byte
#define ICSC1_IREFSTEN _ICSC1.Bits.IREFSTEN
#define ICSC1_IRCLKEN _ICSC1.Bits.IRCLKEN
#define ICSC1_IREFS _ICSC1.Bits.IREFS
#define ICSC1_RDIV0 _ICSC1.Bits.RDIV0
#define ICSC1_RDIV1 _ICSC1.Bits.RDIV1
#define ICSC1_RDIV2 _ICSC1.Bits.RDIV2
#define ICSC1_CLKS0 _ICSC1.Bits.CLKS0
#define ICSC1_CLKS1 _ICSC1.Bits.CLKS1
#define ICSC1_RDIV _ICSC1.MergedBits.grpRDIV
#define ICSC1_CLKS _ICSC1.MergedBits.grpCLKS
#define ICSC1_IREFSTEN_MASK 0x01
#define ICSC1_IRCLKEN_MASK 0x02
#define ICSC1_IREFS_MASK 0x04
#define ICSC1_RDIV0_MASK 0x08
#define ICSC1_RDIV1_MASK 0x10
#define ICSC1_RDIV2_⌨️ 快捷键说明
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