📄 io_map.h
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byte ILT :1; /* Idle Line Type Select */
byte WAKE :1; /* Receiver Wakeup Method Select */
byte M :1; /* 9-Bit or 8-Bit Mode Select */
byte RSRC :1; /* Receiver Source Select */
byte SCISWAI :1; /* SCI Stops in Wait Mode */
byte LOOPS :1; /* Loop Mode Select */
} Bits;
} SCIC1STR;
extern volatile SCIC1STR _SCIC1 @0x00000022;
#define SCIC1 _SCIC1.Byte
#define SCIC1_PT _SCIC1.Bits.PT
#define SCIC1_PE _SCIC1.Bits.PE
#define SCIC1_ILT _SCIC1.Bits.ILT
#define SCIC1_WAKE _SCIC1.Bits.WAKE
#define SCIC1_M _SCIC1.Bits.M
#define SCIC1_RSRC _SCIC1.Bits.RSRC
#define SCIC1_SCISWAI _SCIC1.Bits.SCISWAI
#define SCIC1_LOOPS _SCIC1.Bits.LOOPS
#define SCIC1_PT_MASK 0x01
#define SCIC1_PE_MASK 0x02
#define SCIC1_ILT_MASK 0x04
#define SCIC1_WAKE_MASK 0x08
#define SCIC1_M_MASK 0x10
#define SCIC1_RSRC_MASK 0x20
#define SCIC1_SCISWAI_MASK 0x40
#define SCIC1_LOOPS_MASK 0x80
/*** SCIC2 - SCI Control Register 2; 0x00000023 ***/
typedef union {
byte Byte;
struct {
byte SBK :1; /* Send Break */
byte RWU :1; /* Receiver Wakeup Control */
byte RE :1; /* Receiver Enable */
byte TE :1; /* Transmitter Enable */
byte ILIE :1; /* Idle Line Interrupt Enable (for IDLE) */
byte RIE :1; /* Receiver Interrupt Enable (for RDRF) */
byte TCIE :1; /* Transmission Complete Interrupt Enable (for TC) */
byte TIE :1; /* Transmit Interrupt Enable (for TDRE) */
} Bits;
} SCIC2STR;
extern volatile SCIC2STR _SCIC2 @0x00000023;
#define SCIC2 _SCIC2.Byte
#define SCIC2_SBK _SCIC2.Bits.SBK
#define SCIC2_RWU _SCIC2.Bits.RWU
#define SCIC2_RE _SCIC2.Bits.RE
#define SCIC2_TE _SCIC2.Bits.TE
#define SCIC2_ILIE _SCIC2.Bits.ILIE
#define SCIC2_RIE _SCIC2.Bits.RIE
#define SCIC2_TCIE _SCIC2.Bits.TCIE
#define SCIC2_TIE _SCIC2.Bits.TIE
#define SCIC2_SBK_MASK 0x01
#define SCIC2_RWU_MASK 0x02
#define SCIC2_RE_MASK 0x04
#define SCIC2_TE_MASK 0x08
#define SCIC2_ILIE_MASK 0x10
#define SCIC2_RIE_MASK 0x20
#define SCIC2_TCIE_MASK 0x40
#define SCIC2_TIE_MASK 0x80
/*** SCIS1 - SCI Status Register 1; 0x00000024 ***/
typedef union {
byte Byte;
struct {
byte PF :1; /* Parity Error Flag */
byte FE :1; /* Framing Error Flag */
byte NF :1; /* Noise Flag */
byte OR :1; /* Receiver Overrun Flag */
byte IDLE :1; /* Idle Line Flag */
byte RDRF :1; /* Receive Data Register Full Flag */
byte TC :1; /* Transmission Complete Flag */
byte TDRE :1; /* Transmit Data Register Empty Flag */
} Bits;
} SCIS1STR;
extern volatile SCIS1STR _SCIS1 @0x00000024;
#define SCIS1 _SCIS1.Byte
#define SCIS1_PF _SCIS1.Bits.PF
#define SCIS1_FE _SCIS1.Bits.FE
#define SCIS1_NF _SCIS1.Bits.NF
#define SCIS1_OR _SCIS1.Bits.OR
#define SCIS1_IDLE _SCIS1.Bits.IDLE
#define SCIS1_RDRF _SCIS1.Bits.RDRF
#define SCIS1_TC _SCIS1.Bits.TC
#define SCIS1_TDRE _SCIS1.Bits.TDRE
#define SCIS1_PF_MASK 0x01
#define SCIS1_FE_MASK 0x02
#define SCIS1_NF_MASK 0x04
#define SCIS1_OR_MASK 0x08
#define SCIS1_IDLE_MASK 0x10
#define SCIS1_RDRF_MASK 0x20
#define SCIS1_TC_MASK 0x40
#define SCIS1_TDRE_MASK 0x80
/*** SCIS2 - SCI Status Register 2; 0x00000025 ***/
typedef union {
byte Byte;
struct {
byte RAF :1; /* Receiver Active Flag */
byte :1;
byte BRK13 :1; /* Break Character Length */
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
} Bits;
} SCIS2STR;
extern volatile SCIS2STR _SCIS2 @0x00000025;
#define SCIS2 _SCIS2.Byte
#define SCIS2_RAF _SCIS2.Bits.RAF
#define SCIS2_BRK13 _SCIS2.Bits.BRK13
#define SCIS2_RAF_MASK 0x01
#define SCIS2_BRK13_MASK 0x04
/*** SCIC3 - SCI Control Register 3; 0x00000026 ***/
typedef union {
byte Byte;
struct {
byte PEIE :1; /* Parity Error Interrupt Enable */
byte FEIE :1; /* Framing Error Interrupt Enable */
byte NEIE :1; /* Noise Error Interrupt Enable */
byte ORIE :1; /* Overrun Interrupt Enable */
byte TXINV :1; /* Transmit Data Inversion */
byte TXDIR :1; /* TxD Pin Direction in Single-Wire Mode */
byte T8 :1; /* Ninth Data Bit for Transmitter */
byte R8 :1; /* Ninth Data Bit for Receiver */
} Bits;
} SCIC3STR;
extern volatile SCIC3STR _SCIC3 @0x00000026;
#define SCIC3 _SCIC3.Byte
#define SCIC3_PEIE _SCIC3.Bits.PEIE
#define SCIC3_FEIE _SCIC3.Bits.FEIE
#define SCIC3_NEIE _SCIC3.Bits.NEIE
#define SCIC3_ORIE _SCIC3.Bits.ORIE
#define SCIC3_TXINV _SCIC3.Bits.TXINV
#define SCIC3_TXDIR _SCIC3.Bits.TXDIR
#define SCIC3_T8 _SCIC3.Bits.T8
#define SCIC3_R8 _SCIC3.Bits.R8
#define SCIC3_PEIE_MASK 0x01
#define SCIC3_FEIE_MASK 0x02
#define SCIC3_NEIE_MASK 0x04
#define SCIC3_ORIE_MASK 0x08
#define SCIC3_TXINV_MASK 0x10
#define SCIC3_TXDIR_MASK 0x20
#define SCIC3_T8_MASK 0x40
#define SCIC3_R8_MASK 0x80
/*** SCID - SCI Data Register; 0x00000027 ***/
typedef union {
byte Byte;
struct {
byte R0_T0 :1; /* Receive/Transmit Data Bit 0 */
byte R1_T1 :1; /* Receive/Transmit Data Bit 1 */
byte R2_T2 :1; /* Receive/Transmit Data Bit 2 */
byte R3_T3 :1; /* Receive/Transmit Data Bit 3 */
byte R4_T4 :1; /* Receive/Transmit Data Bit 4 */
byte R5_T5 :1; /* Receive/Transmit Data Bit 5 */
byte R6_T6 :1; /* Receive/Transmit Data Bit 6 */
byte R7_T7 :1; /* Receive/Transmit Data Bit 7 */
} Bits;
} SCIDSTR;
extern volatile SCIDSTR _SCID @0x00000027;
#define SCID _SCID.Byte
#define SCID_R0_T0 _SCID.Bits.R0_T0
#define SCID_R1_T1 _SCID.Bits.R1_T1
#define SCID_R2_T2 _SCID.Bits.R2_T2
#define SCID_R3_T3 _SCID.Bits.R3_T3
#define SCID_R4_T4 _SCID.Bits.R4_T4
#define SCID_R5_T5 _SCID.Bits.R5_T5
#define SCID_R6_T6 _SCID.Bits.R6_T6
#define SCID_R7_T7 _SCID.Bits.R7_T7
#define SCID_R0_T0_MASK 0x01
#define SCID_R1_T1_MASK 0x02
#define SCID_R2_T2_MASK 0x04
#define SCID_R3_T3_MASK 0x08
#define SCID_R4_T4_MASK 0x10
#define SCID_R5_T5_MASK 0x20
#define SCID_R6_T6_MASK 0x40
#define SCID_R7_T7_MASK 0x80
/*** SPIC1 - SPI Control Register 1; 0x00000028 ***/
typedef union {
byte Byte;
struct {
byte LSBFE :1; /* LSB First (shifter direction) */
byte SSOE :1; /* Slave Select Output Enable */
byte CPHA :1; /* Clock Phase */
byte CPOL :1; /* Clock Polarity */
byte MSTR :1; /* Master/Slave Mode Select */
byte SPTIE :1; /* SPI Transmit Interrupt Enable */
byte SPE :1; /* SPI System Enable */
byte SPIE :1; /* SPI Interrupt Enable */
} Bits;
} SPIC1STR;
extern volatile SPIC1STR _SPIC1 @0x00000028;
#define SPIC1 _SPIC1.Byte
#define SPIC1_LSBFE _SPIC1.Bits.LSBFE
#define SPIC1_SSOE _SPIC1.Bits.SSOE
#define SPIC1_CPHA _SPIC1.Bits.CPHA
#define SPIC1_CPOL _SPIC1.Bits.CPOL
#define SPIC1_MSTR _SPIC1.Bits.MSTR
#define SPIC1_SPTIE _SPIC1.Bits.SPTIE
#define SPIC1_SPE _SPIC1.Bits.SPE
#define SPIC1_SPIE _SPIC1.Bits.SPIE
#define SPIC1_LSBFE_MASK 0x01
#define SPIC1_SSOE_MASK 0x02
#define SPIC1_CPHA_MASK 0x04
#define SPIC1_CPOL_MASK 0x08
#define SPIC1_MSTR_MASK 0x10
#define SPIC1_SPTIE_MASK 0x20
#define SPIC1_SPE_MASK 0x40
#define SPIC1_SPIE_MASK 0x80
/*** SPIC2 - SPI Control Register 2; 0x00000029 ***/
typedef union {
byte Byte;
struct {
byte SPC0 :1; /* SPI Pin Control 0 */
byte SPISWAI :1; /* SPI Stop in Wait Mode */
byte :1;
byte BIDIROE :1; /* Bidirectional Mode Output Enable */
byte MODFEN :1; /* Master Mode-Fault Function Enable */
byte :1;
byte :1;
byte :1;
} Bits;
} SPIC2STR;
extern volatile SPIC2STR _SPIC2 @0x00000029;
#define SPIC2 _SPIC2.Byte
#define SPIC2_SPC0 _SPIC2.Bits.SPC0
#define SPIC2_SPISWAI _SPIC2.Bits.SPISWAI
#define SPIC2_BIDIROE _SPIC2.Bits.BIDIROE
#define SPIC2_MODFEN _SPIC2.Bits.MODFEN
#define SPIC2_SPC0_MASK 0x01
#define SPIC2_SPISWAI_MASK 0x02
#define SPIC2_BIDIROE_MASK 0x08
#define SPIC2_MODFEN_MASK 0x10
/*** SPIBR - SPI Baud Rate Register; 0x0000002A ***/
typedef union {
byte Byte;
struct {
byte SPR0 :1; /* SPI Baud Rate Divisor Bit 0 */
byte SPR1 :1; /* SPI Baud Rate Divisor Bit 1 */
byte SPR2 :1; /* SPI Baud Rate Divisor Bit 2 */
byte :1;
byte SPPR0 :1; /* SPI Baud Rate Prescale Divisor Bit 0 */
byte SPPR1 :1; /* SPI Baud Rate Prescale Divisor Bit 1 */
byte SPPR2 :1; /* SPI Baud Rate Prescale Divisor Bit 2 */
byte :1;
} Bits;
struct {
byte grpSPR :3;
byte :1;
byte grpSPPR :3;
byte :1;
} MergedBits;
} SPIBRSTR;
extern volatile SPIBRSTR _SPIBR @0x0000002A;
#define SPIBR _SPIBR.Byte
#define SPIBR_SPR0 _SPIBR.Bits.SPR0
#define SPIBR_SPR1 _SPIBR.Bits.SPR1
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