📄 c240.h
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#define IMR (* (volatile unsigned int *) 0x04) /* Interrupt Mask Register*/
#define GREG (* (volatile unsigned int *) 0x05) /* Global memory allocation Register */
#define IFR (* (volatile unsigned int *) 0x06) /* Interrupt Flag Register */
/* System configuration and interrupt registers */
#define SYSCR (* (volatile unsigned int *) 0x7018) /* System Module Control Register X240 only*/
#define SYSSR (* (volatile unsigned int *) 0x701A) /* System Module Status Register X240 only*/
#define SYSIVR (* (volatile unsigned int *) 0x701E) /* System Interrupt Vector Register X240 only*/
/* PLL configuration registers */
#define CKCR0 (* (volatile unsigned int *) 0x702a) /* PLL Clock Control Register 0 X240 only*/
#define PLL_CNTL1 (* (volatile unsigned int *) 0x702a)
#define CKCR1 (* (volatile unsigned int *) 0x702c) /* PLL Clock Control Register 1 X240 only*/
#define PLL_CNTL2 (* (volatile unsigned int *) 0x702c)
/* External interrupt configuration registers */
#define XINT1CR (* (volatile unsigned int *) 0x7070) /* Int1 (type A) Control reg for X240 only*/
#define NMICR (* (volatile unsigned int *) 0x7072) /* Non maskable Int (type A) Control reg X240 only*/
#define XINT2CR240 (* (volatile unsigned int *) 0x7078) /* Int2 (type C) Control reg X240 only*/
#define XINT3CR (* (volatile unsigned int *) 0x707A) /* Int3 (type C) Control reg X240 only*/
/* Digital I/O registers */
#define OCRA (* (volatile unsigned int *) 0x7090) /* Output Control Reg A */
#define OCRB (* (volatile unsigned int *) 0x7092) /* Output Control Reg B */
#define OPCRA (* (volatile unsigned int *) 0x7090) /* Output Control Reg A */
#define OPCRB (* (volatile unsigned int *) 0x7092) /* Output Control Reg B */
#define ISRA (* (volatile unsigned int *) 0x7094) /*Input Status Reg A X240 only */
#define ISRB (* (volatile unsigned int *) 0x7096) /*Input Status Reg B X240 only */
#define PADATDIR (* (volatile unsigned int *) 0x7098) /* I/O port A Data & Direction reg*/
#define PBDATDIR (* (volatile unsigned int *) 0x709A) /* I/O port B Data & Direction reg*/
#define PCDATDIR (* (volatile unsigned int *) 0x709C) /* I/O port C Data & Direction reg*/
#define PDDATDIR (* (volatile unsigned int *) 0x709E) /* I/O port D Data & Direction reg*/
#define WDCNTR (* (volatile unsigned int *) 0x7023) /* WD Counter reg */
#define WDKEY (* (volatile unsigned int *) 0x7025) /* WD Key reg */
#define WD_KEY (* (volatile unsigned int *) 0x7025)
#define WDCR (* (volatile unsigned int *) 0x7029) /* WD Control reg */
#define WD_CNTL (* (volatile unsigned int *) 0x7029)
#define RTICNTR (* (volatile unsigned int *) 0x7021) /* RTI counter reg X240 only*/
#define RTICR (* (volatile unsigned int *) 0x7027) /* RTI control reg X240 only*/
#define ADCTRL1 (* (volatile unsigned int *) 0x7032) /* ADC Control Reg1 */
#define ADCTRL2 (* (volatile unsigned int *) 0x7034) /* ADC Control Reg2 */
#define ADCFIFO1 (* (volatile unsigned int *) 0x7036) /* ADC DATA REG FIFO for ADC1 */
#define ADCFIFO2 (* (volatile unsigned int *) 0x7038) /* ADC DATA REG FIFO for ADC2 */
#define ADC_CNTL1 (* (volatile unsigned int *) 0x07032) /*ADC Control & Status reg */
#define ADC_CNTL2 (* (volatile unsigned int *) 0x07034) /*ADC Configuration reg */
#define ADC_FIFO1 (* (volatile unsigned int *) 0x07036) /*ADC C)annel 0 Result Data */
#define ADC_FIFO2 (* (volatile unsigned int *) 0x07038) /*ADC C)annel 1 Result Data */
#define SPICCR (* (volatile unsigned int *) 0x7040) /* SPI Config Control Reg */
#define SPICTL (* (volatile unsigned int *) 0x7041) /* SPI Operation Control Reg */
#define SPISTS (* (volatile unsigned int *) 0x7042) /* SPI Status Reg */
#define SPIBRR (* (volatile unsigned int *) 0x7044) /* SPI Baud rate control reg */
#define SPIRXEMU (* (volatile unsigned int *) 0x7046) /* SPI Emulation buffer reg */
#define SPIRXBUF (* (volatile unsigned int *) 0x7047) /* SPI Serial receive buffer reg */
#define SPITXBUF (* (volatile unsigned int *) 0x7048) /* SPI Serial transmit buffer reg */
#define SPIDAT (* (volatile unsigned int *) 0x7049) /* SPI Serial data reg */
#define SPIPC1 (* (volatile unsigned int *) 0x704D) /* SPI Port Control Register 1 X240 only*/
#define SPIPC2 (* (volatile unsigned int *) 0x704E) /* SPI Port Control Register 2 X240 only*/
#define SPIPRI (* (volatile unsigned int *) 0x704F) /* SPI Priority control reg */
#define SCICCR (* (volatile unsigned int *) 0x7050) /* SCI Communication control reg */
#define SCICTL1 (* (volatile unsigned int *) 0x7051) /* SCI Control reg1 */
#define SCIHBAUD (* (volatile unsigned int *) 0x7052) /* SCI Baud Rate MSbyte reg */
#define SCILBAUD (* (volatile unsigned int *) 0x7053) /* SCI Baud Rate LSbyte reg */
#define SCICTL2 (* (volatile unsigned int *) 0x7054) /* SCI Control reg2 */
#define SCIRXST (* (volatile unsigned int *) 0x7055) /* SCI Receiver Status reg */
#define SCIRXEMU (* (volatile unsigned int *) 0x7056) /* SCI Emulation Data Buffer reg */
#define SCIRXBUF (* (volatile unsigned int *) 0x7057) /* SCI Receiver Data buffer reg */
#define SCITXBUF (* (volatile unsigned int *) 0x7059) /* SCI Transmit Data buffer reg */
#define SCIPC2 (* (volatile unsigned int *) 0x705E) /* SCI Port Control reg2 (X240 only) */
#define SCIPRI (* (volatile unsigned int *) 0x705F) /* SCI Priority control reg */
/* Event Manager (EV) registers */
#define GPTCON (* (volatile unsigned int *) 0x7400) /* GP Timer control register*/
#define T1CNT (* (volatile unsigned int *) 0x7401) /* GP Timer 1 counter register*/
#define T1CMPR (* (volatile unsigned int *) 0x7402) /* GP Timer 1 compare register*/
#define T1CMP (* (volatile unsigned int *) 0x7402)
#define T1PR (* (volatile unsigned int *) 0x7403) /* GP Timer 1 period register*/
#define T1PER (* (volatile unsigned int *) 0x7403)
#define T1CON (* (volatile unsigned int *) 0x7404) /* GP Timer 1 control register*/
#define T2CNT (* (volatile unsigned int *) 0x7405) /* GP Timer 2 counter register*/
#define T2CMPR (* (volatile unsigned int *) 0x7406) /* GP Timer 2 compare register*/
#define T2CMP (* (volatile unsigned int *) 0x7406)
#define T2PR (* (volatile unsigned int *) 0x7407) /* GP Timer 2 period register*/
#define T2PER (* (volatile unsigned int *) 0x7407)
#define T2CON (* (volatile unsigned int *) 0x7408) /* GP Timer 2 control register */
#define T3CNT (* (volatile unsigned int *) 0x7409) /* GP Timer 3 counter register X240 only*/
#define T3CMPR (* (volatile unsigned int *) 0x740A) /* GP Timer 3 compare register X240 only*/
#define T3CMP (* (volatile unsigned int *) 0x740A)
#define T3PR (* (volatile unsigned int *) 0x740B) /* GP Timer 3 period register X240 only*/
#define T3PER (* (volatile unsigned int *) 0x740B)
#define T3CON (* (volatile unsigned int *) 0x740C) /* GP Timer 3 control register X240 only*/
#define COMCON (* (volatile unsigned int *) 0x7411) /* Compare control register*/
#define ACTR (* (volatile unsigned int *) 0x7413) /* Full compare action control register*/
#define SACTR (* (volatile unsigned int *) 0x7414) /* Simple compare action control register*/
#define DBTCON (* (volatile unsigned int *) 0x7415) /* Dead-band timer control register*/
#define CMPR1 (* (volatile unsigned int *) 0x7417) /* Full compare unit compare register1*/
#define CMPR2 (* (volatile unsigned int *) 0x7418) /* Full compare unit compare register2*/
#define CMPR3 (* (volatile unsigned int *) 0x7419) /* Full compare unit compare register3*/
#define SCMPR1 (* (volatile unsigned int *) 0x741A) /* Single compare unit compare register1 X240 only*/
#define SCMPR2 (* (volatile unsigned int *) 0x741B) /* Single compare unit compare register2 X240 only*/
#define SCMPR3 (* (volatile unsigned int *) 0x741C) /* Single compare unit compare register3 X240 only*/
#define CAPCON (* (volatile unsigned int *) 0x7420) /* Capture control register*/
#define CAPFIFO (* (volatile unsigned int *) 0x7422) /* Capture FIFO status register*/
#define FIFO1 (* (volatile unsigned int *) 0x7423) /* Capture C)annel 1 FIFO Top */
#define FIFO2 (* (volatile unsigned int *) 0x7424) /* Capture C)annel 2 FIFO Top */
#define FIFO3 (* (volatile unsigned int *) 0x7425) /* Capture C)annel 3 FIFO Top */
#define FIFO4 (* (volatile unsigned int *) 0x7426) /* Capture C)annel 4 FIFO Top X240 only*/
#define CAP1FIFO (* (volatile unsigned int *) 0x7423) /* Capture C)annel 1 FIFO Top */
#define CAP2FIFO (* (volatile unsigned int *) 0x7424) /* Capture C)annel 2 FIFO Top */
#define CAP3FIFO (* (volatile unsigned int *) 0x7425) /* Capture C)annel 3 FIFO Top */
#define CAP4FIFO (* (volatile unsigned int *) 0x7426) /* Capture C)annel 4 FIFO Top X240 only*/
#define EVIMRA (* (volatile unsigned int *) 0x742C) /* Group A Interrupt Mask Register */
#define EVIMRB (* (volatile unsigned int *) 0x742D) /* Group B Interrupt Mask Register */
#define EVIMRC (* (volatile unsigned int *) 0x742E) /* Group C Interrupt Mask Register */
#define IMRA (* (volatile unsigned int *) 0x742C) /* Group A Interrupt Mask Register */
#define IMRB (* (volatile unsigned int *) 0x742D) /* Group B Interrupt Mask Register */
#define IMRC (* (volatile unsigned int *) 0x742E) /* Group C Interrupt Mask Register */
#define EVIFRA (* (volatile unsigned int *) 0x742F) /* Group A Interrupt Flag Register */
#define EVIFRB (* (volatile unsigned int *) 0x7430) /* Group B Interrupt Flag Register */
#define EVIFRC (* (volatile unsigned int *) 0x7431) /* Group C Interrupt Flag Register */
#define IFRA (* (volatile unsigned int *) 0x742F) /* Group A Interrupt Flag Register */
#define IFRB (* (volatile unsigned int *) 0x7430) /* Group B Interrupt Flag Register */
#define IFRC (* (volatile unsigned int *) 0x7431) /* Group C Interrupt Flag Register */
#define EVIVRA (* (volatile unsigned int *) 0x7432) /* Group A Int Vector Register X240 only*/
#define EVIVRB (* (volatile unsigned int *) 0x7433) /* Group B Int Vector Register X240 only*/
#define EVIVRC (* (volatile unsigned int *) 0x7434)
#define WSGR (* (volatile unsigned int *) 0x0FFFF)⌨️ 快捷键说明
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