📄 main0504.c
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#include "C240.h"
/* define constant value */
#define FALSE 0
#define TRUE 1
#define VELOCITY_CONST 1562500 /* Velocity contant */
/* define variable */
unsigned int CAP_A;
unsigned int CAP_B;
unsigned int CAP_C;
unsigned int IA_max,IB_max,IC_max; /* MAX limit for current */
unsigned int IA_min,IB_min,IC_min; /* MIN limit for current */
unsigned int I_MIN,I_MAX;
unsigned int ADC_channel; /* Channel for A/D convert */
static unsigned int PBvalue[6];
int display_times; /* accumulation for display */
int capture1,capture2,capture3 ;
int CAP1_flag;
int input_state;
int sign_state ; /* 1 is clockwise,0 is anticlockwise */
int dot_state;
int inputdata_num; /* number of input data */
int start_mode;
int T3overflow_counter; /* T3 overflow times */
unsigned int angle_on; /* fire angle */
unsigned int angle_off; /* cut off angle */
unsigned int angle;
unsigned int input_value; /* input data value */
unsigned int input_dotbit; /* the radix bit of input data value */
unsigned int position_value; /* the display value of position */
unsigned int position_dotbit; /* the radix bit of position's display value */
unsigned int position; /* the value of position */
unsigned int velocity_value; /* the display value of velocity */
unsigned int velocity_dotbit; /* the radix bit of velocity's display value */
int display_order=1; /* 1 while display velocity ,2 while display current ,3 while display input data */
/* define Input/Output variable value */
ioport unsigned int port0,port1,port2,port3,port4,port5;
/* define structure type and variable value */
struct CAP_INT
{
unsigned int PB_value; /* the value of I/O port B */
unsigned int CAP_value; /* the capture value of CAP unit */
unsigned long delta_count; /* the delta value of 2 times ajacent capture value */
int phase_A;
struct CAP_INT * next;
};
struct CAP_INT * CAP_p,* angle_p;
/*********************************************/
/* Creat circle linkage table for CAP */
struct CAP_INT * creat_link()
{
int i;
struct CAP_INT * h,* p; /* pointer h point to virtual value */
h=(struct CAP_INT *)malloc(sizeof(struct CAP_INT));
h->next=h;
for(i=1;i<=5;i++)
{
p=(struct CAP_INT *)malloc(sizeof(struct CAP_INT));
p->PB_value=0;
p->CAP_value=0;
p->delta_count=0;
p->phase_A=FALSE;
p->next=h->next;
h->next=p;
}
return (h); /* return head pointer */
}
/*********************************************/
/*********************************************/
void dsp_setup()
{
unsigned int temp;
/*********************************************/
/* Disable watchdog timer */
/*********************************************/
temp = WDCR;
temp = temp|0x68;
WDCR = temp;
/*********************************************/
/* initialize PLL module (20 MHz XTAL1) */
/*********************************************/
CKCR1 = 0x60; /* crystal=20MHz CPUCLK = 20MHz */
/* and 1x PLL mult ratio */
CKCR0 = 0xc3; /* low–power mode 0, */
/* ACLK enabled, */
/* PLL enabled, */
/* SYSCLK=CPUCLK/2 */
SYSCR = 0x40c0;
XINT1CR=0x0007;
}
/* Initiate the event management register */
void eventmgr_init()
{
GPTCON=0x0442;
/* Initialize PWM */
/* Period is 200us */
ACTR=0x09aa;
CMPR1=0x03e8;
CMPR2=0x03e8;
CMPR3=0x03e8;
DBTCON=0x0000;
COMCON=0x4a57;
COMCON=0xca57;
T1PER=0xfa0;
T1CON=0x0000;
T1CON=0x910e;
/* Initial timer 2 */
T2CNT=0x00;
T2PER=0x00c8; /* T2PER=200 ,ADC period is 20us*/
T2CON=0x9100;
/* Setup shared pins */
OCRA = 0xf800; /* pins IOPB0–IOPB3 & IOPA0–IOPA2 to I/O pins */
OCRB = 0x00f1; /* pins are: ADSOC, XF, /BIO, CAP1–CAP4 */
PADATDIR = 0x0707; /* outputs IOPA0–IOPA2, set low */
PBDATDIR = 0x0704; /* outputs IOPB0–IOPB2, set high */
/* Initialize T3 */
T3CNT=0x0;
T3PER=0xffff;
T3CON=0x9440; /* Prescaler=/16 */
/* Setup capture units */
CAPCON = 0x0; /* reset capture control register */
CAPFIFO= 0x0ff; /* Clear FIFO’s */
CAPCON = 0xb6fc; /* enable #123, use Timer3, both edges */
/* Setup ADC units */
ADCTRL1=0xcb04; /* enable ADC1,use channel 2,and enable ADCINT */
ADCTRL2=0x0404;
T1CON=0x914e; /* enable PWM output */
}
/*******************************************************************/
void disable_interrupts()
{
asm(" SETC INTM");
}
/************************************************************************/
void enable_interrupts()
{
IFR = 0xffff; /* Clear pending interrupts */
IFRA = 0xffff;
IFRB = 0xffff;
IFRC = 0xffff;
IMR = 0x002e; /* Enable CPU Interrupts:INT 2,3,4 */
IMRA = 0x0080; /* Enable timer 1 period interrupts */
IMRB = 0x0010; /* Enable timer 3 period and compare interrupts */
IMRC = 0x0007; /* Enable CAP1 interrupts*/
asm(" CLRC INTM"); /* Global interrupt enable */
}
/* initiating parameter and register */
void init_SRM()
{
velocity_value=0;
velocity_dotbit=4;
position_value=position=0;
T3overflow_counter=0;
position_dotbit=4;
input_value=0;
input_dotbit=4;
display_times=0;
input_state=FALSE;
sign_state=0;
dot_state=FALSE;
display_order=3;
inputdata_num=0;
start_mode=TRUE;
ADC_channel=2;
I_MAX=550; /* The relative current is 2.5A */
I_MIN=542; /* The relative current is 2A */
capture1=capture2=capture3=1;
CAP1_flag=0;
}
/********************************************************** */
/* READ CAPTURE FIFO REGISTERS
/* This routine is used to read the data from the capture FIFO
/* registers.
/*
/* inputs: capture = which FIFO to read?
/* range = 1–3
/* outputs fifo_data =
/* range = 0–65535
/********************************************************* */
unsigned int read_fifo(int capture)
{
unsigned int fifo_data;
int fifo_status;
if (capture == 1)
{
do {
fifo_data = FIFO1; /* read value */
fifo_status = CAPFIFO & 0x0300; /* read status register, mask bits */
}
while (fifo_status != 0);
}
else if (capture == 2)
{
do {
fifo_data = FIFO2; /* read value */
fifo_status = CAPFIFO & 0x0c00; /* read status register, mask bits */
}
while (fifo_status != 0);
}
else if (capture == 3)
{
do {
fifo_data = FIFO3; /* read value */
fifo_status = CAPFIFO & 0x3000; /* read status register, mask bits */
}
while (fifo_status != 0);
}
else
fifo_data = 0xffff; /* error, not a valid capture */
return fifo_data;
}
/* ISR for GPT1 interrupt */
void c_int2()
{
IFR=0x0002; /* clear CPU interrupt flag */
IFRA=0x7ff;
display_times++;
}
/* ISR for GPT3 interrupt */
void c_int3()
{
int groupb_flags;
IFR=0x0004; /* clear CPU interrupt flag */
groupb_flags=IFRB;
if (groupb_flags & 0x20) /* if GPT3 compare interrupt */
{
IFRB=0x0ef; /* clear interrupt flag */
CAP_p=CAP_p->next;
PBDATDIR=CAP_p->PB_value;
if (angle==1)
{
angle=2;
T3CMP= angle_off;
T3CON=0x944a;
CAP_p->delta_count=0;
}
else
{
IMRB = 0x0010;
T3CON=0x9440; /* Disable timer 3 */
angle=3;
}
}
else if (groupb_flags & 0x10) /* if GPT3 period interrupt */
{
IFRB=0x0df; /* clear interrupt flag */
T3overflow_counter++;
}
else
IFRB=0x0ff; /* not a valid interrupt */
}
/* ISR for CAP unit interrupt */
void c_int4()
{
int groupc_flags;
int capture;
struct CAP_INT * p;
IFR=0x0008; /* clear CPU interrupt flag */
groupc_flags = IFRC; /* read event manger interrupt */
/* flag register */
if ((groupc_flags & 0x07)==0)
{
/* not a valid capture */
IFRC = 0xff;
capture = 0;
}
p=CAP_p;
CAP_p=CAP_p->next;
if (groupc_flags & 0x1)
{
/* capture #1 */
IFRC = 0xf9; /* clear flag register */
capture = 1;
if (CAP1_flag)
{
if (CAP_A)
CAP_A=0;
else
CAP_A=1;
PBDATDIR=PBvalue[CAP_A];
}
}
else if (groupc_flags & 0x2)
{
/* capture #2 */
IFRC = 0xfa;
capture = 2;
CAP1_flag=TRUE;
if (CAP_B)
CAP_B=0;
else
CAP_B=1;
PBDATDIR=PBvalue[CAP_B+2];
}
else if (groupc_flags & 0x4)
{
/* capture #3 */
IFRC = 0xfc;
capture = 3;
CAP1_flag=TRUE;
if (CAP_C)
CAP_C=0;
else
CAP_C=1;
PBDATDIR=PBvalue[CAP_C+4];
}
CAP_p->CAP_value = read_fifo(capture); /* read FIFO */
CAP_p->delta_count=65536*T3overflow_counter+CAP_p->CAP_value-p->delta_count;
T3overflow_counter=0;
position=position+75; /* accumulate position */
}
/*************************************/
//*************************************/
/* drive SRM */
void drive_SRM()
{
static unsigned int clock_PBvalue[6]={0x0703,0x0704,0x0706,0x0701,0x0702,0x0705};
static unsigned int anticlock_PBvalue[6]={0x0705,0x0702,0x0704,0x0703,0x0706,0x0701};
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