f240.h

是用于开关磁阻电机的位置伺服控制的C语言源代码,基于CCS的开发环境.希望可以对你有所帮助.

  IMR			.set   0004h		/* Interrupt Mask Register*/
  GREG			.set   0005h		/* Global memory allocation Register */
  IFR			.set   0006h		/* Interrupt Flag Register */

/* System configuration and interrupt registers */
  SYSCR			.set   7018h		/* System Module Control Register X240 only*/
  SYSSR			.set   701Ah		/* System Module Status Register X240 only*/
  SYSIVR		.set   701Eh		/* System Interrupt Vector Register X240 only*/

/* PLL configuration registers */
  CKCR0			.set   702ah		/* PLL Clock Control Register 0 X240 only*/
  PLL_CNTL1		.set   702ah
  CKCR1			.set   702ch		/* PLL Clock Control Register 1 X240 only*/
  PLL_CNTL2		.set   702ch
/*  External interrupt configuration registers */
  XINT1CR		.set   7070h		/* Int1 (type A) Control reg for X240 only*/
  NMICR			.set   7072h		/* Non maskable Int (type A) Control reg X240 only*/
  XINT2CR240	.set   7078h		/* Int2 (type C) Control reg X240 only*/
  XINT3CR		.set   707Ah		/* Int3 (type C) Control reg X240 only*/

/* Digital I/O registers */
  OCRA			.set   7090h		/* Output Control Reg A  */
  OCRB			.set   7092h		/* Output Control Reg B  */
  OPCRA			.set   7090h		/* Output Control Reg A  */
  OPCRB			.set   7092h		/* Output Control Reg B  */
  ISRA 			.set   7094h	/*Input Status Reg A X240 only  */
  ISRB 			.set   7096h	/*Input Status Reg B X240 only  */
  PADATDIR		.set   7098h		/* I/O port A Data & Direction reg*/
  PBDATDIR		.set   709Ah		/* I/O port B Data & Direction reg*/
  PCDATDIR		.set   709Ch		/* I/O port C Data & Direction reg*/
  PDDATDIR		.set   709Eh		/* I/O port D Data & Direction reg*/

/* Watchdog (WD) registers */
  WDCNTR		.set   7023h		/* WD Counter reg */
  WDKEY			.set   7025h		/* WD Key reg */
  WD_KEY		.set   7025h
  WDCR			.set   7029h		/* WD Control reg */
  WD_CNTL     	.set   7029h 
  RTICNTR		.set   7021h		/* RTI counter reg X240 only*/
  RTICR			.set   7027h		/* RTI control reg X240 only*/
  ADCTRL1		.set   7032h		/* ADC Control Reg1 */
  ADCTRL2		.set   7034h		/* ADC Control Reg2 */
  ADCFIFO1		.set   7036h		/* ADC DATA REG FIFO for ADC1  */
  ADCFIFO2		.set   7038h		/* ADC DATA REG FIFO for ADC2  */
  ADC_CNTL1   	.set   07032h          /*ADC Control & Status reg  */
  ADC_CNTL2   	.set   07034h          /*ADC Configuration reg     */
  ADC_FIFO1   	.set   07036h          /*ADC Channel 0 Result Data   */
  ADC_FIFO2   	.set   07038h          /*ADC Channel 1 Result Data   */
  SPICCR		.set   7040h		/* SPI Config Control Reg             */
  SPICTL		.set   7041h		/* SPI Operation Control Reg          */
  SPISTS		.set   7042h		/* SPI Status Reg                       */
  SPIBRR		.set   7044h		/* SPI Baud rate control reg         */
  SPIRXEMU		.set   7046h		/* SPI Emulation buffer reg       */
  SPIRXBUF		.set   7047h		/* SPI Serial receive buffer reg   */
  SPITXBUF		.set   7048h		/* SPI Serial transmit buffer reg   */
  SPIDAT		.set   7049h		/* SPI Serial data reg      */
  SPIPC1		.set   704Dh		/* SPI Port Control Register 1 X240 only*/
  SPIPC2		.set   704Eh		/* SPI Port Control Register 2 X240 only*/
  SPIPRI		.set   704Fh		/* SPI Priority control reg   */
  SCICCR		.set   7050h		/* SCI Communication control reg */
  SCICTL1		.set   7051h		/* SCI Control reg1              */
  SCIHBAUD		.set   7052h		/* SCI Baud Rate MSbyte reg   */
  SCILBAUD		.set   7053h		/* SCI Baud Rate LSbyte reg   */
  SCICTL2		.set   7054h		/* SCI Control reg2               */
  SCIRXST		.set   7055h		/* SCI Receiver Status reg        */
  SCIRXEMU		.set   7056h		/* SCI Emulation Data Buffer reg  */
  SCIRXBUF		.set   7057h		/* SCI Receiver Data buffer reg   */
  SCITXBUF		.set   7059h		/* SCI Transmit Data buffer reg   */
  SCIPC2		.set   705Eh		/* SCI Port Control reg2 (X240 only)   */
  SCIPRI		.set   705Fh		/* SCI Priority control reg            */

/* Event Manager (EV) registers  */
  GPTCON		.set   7400h		/* GP Timer control register*/ 
  T1CNT			.set   7401h		/* GP Timer 1 counter register*/ 
  T1CMPR		.set   7402h		/* GP Timer 1 compare register*/ 
  T1CMP			.set   7402h
  T1PR			.set   7403h		/* GP Timer 1 period register*/ 
  T1PER			.set   7403h
  T1CON			.set   7404h		/* GP Timer 1 control register*/ 
  T2CNT			.set   7405h		/* GP Timer 2 counter register*/ 
  T2CMPR		.set   7406h		/* GP Timer 2 compare register*/ 
  T2CMP			.set   7406h
  T2PR			.set   7407h		/* GP Timer 2 period register*/ 
  T2PER			.set   7407h
  T2CON			.set   7408h		/* GP Timer 2 control register   */
  T3CNT			.set   7409h		/* GP Timer 3 counter register X240 only*/
  T3CMPR		.set   740Ah		/* GP Timer 3 compare register  X240 only*/
  T3CMP			.set   740Ah
  T3PR			.set   740Bh		/* GP Timer 3 period register  X240 only*/
  T3PER			.set   740Bh	
  T3CON			.set   740Ch		/* GP Timer 3 control register X240 only*/
                           
  COMCON	    .set   7411h		/* Compare control register*/
  ACTR			.set   7413h		/* Full compare action control register*/
  SACTR			.set   7414h		/* Simple compare action control register*/ 
  DBTCON	    .set   7415h		/* Dead-band timer control register*/ 
                          
  CMPR1			.set   7417h		/* Full compare unit compare register1*/ 
  CMPR2			.set   7418h		/* Full compare unit compare register2*/
  CMPR3			.set   7419h		/* Full compare unit compare register3*/
                          
  SCMPR1	    .set   741Ah		/* Single compare unit compare register1 X240 only*/
  SCMPR2	    .set   741Bh		/* Single compare unit compare register2 X240 only*/
  SCMPR3	    .set   741Ch		/* Single compare unit compare register3 X240 only*/
  CAPCON	    .set   7420h		/* Capture control register*/ 
  CAPFIFO 		.set   7422h		/* Capture FIFO status register*/ 
			              
  FIFO1			.set   7423h		/* Capture Channel 1 FIFO Top      */
  FIFO2			.set   7424h		/* Capture Channel 2 FIFO Top      */
  FIFO3			.set   7425h		/* Capture Channel 3 FIFO Top      */
  FIFO4			.set   7426h		/* Capture Channel 4 FIFO Top X240 only*/
  CAP1FIFO		.set   7423h		/* Capture Channel 1 FIFO Top      */
  CAP2FIFO		.set   7424h		/* Capture Channel 2 FIFO Top     */
  CAP3FIFO		.set   7425h		/* Capture Channel 3 FIFO Top      */
  CAP4FIFO		.set   7426h		/* Capture Channel 4 FIFO Top X240 only*/

  EVIMRA	    .set   742Ch		/* Group A Interrupt Mask Register      */
  EVIMRB	    .set   742Dh		/* Group B Interrupt Mask Register      */
  EVIMRC	    .set   742Eh		/* Group C Interrupt Mask Register      */
  IMRA		    .set   742Ch		/* Group A Interrupt Mask Register      */
  IMRB		    .set   742Dh		/* Group B Interrupt Mask Register      */
  IMRC			.set   742Eh		/* Group C Interrupt Mask Register      */


  EVIFRA		.set   742Fh		/* Group A Interrupt Flag Register      */
  EVIFRB		.set   7430h		/* Group B Interrupt Flag Register      */
  EVIFRC		.set   7431h		/* Group C Interrupt Flag Register      */
  IFRA			.set   742Fh		/* Group A Interrupt Flag Register      */
  IFRB			.set   7430h		/* Group B Interrupt Flag Register      */
  IFRC			.set   7431h		/* Group C Interrupt Flag Register      */
                                                                  
 
  EVIVRA		.set   7432h		/* Group A Int Vector Register X240 only*/
  EVIVRB		.set   7433h		/* Group B Int Vector Register X240 only*/
  EVIVRC		.set   7434h		/* Group C Int Vector Register X240 only*/