📄 reset.c
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reset_vpp_par();
//
// postlog
#ifdef PMP_MCU810 ////////add to wirte IR head H/L and keycode --yangli 2004-11-11
SendIRIDPowerKeyToMCU();
#endif
#ifdef PMP_Video_Onlycvbs ///yangli 2004-11-29.add to pmp video out only cvbs
tv_dacoff(TV_DAC_B|TV_DAC_C|TV_DAC_D|TV_DAC_E|TV_DAC_F);//only cvb is on
#endif
#ifdef IC_8202E
regs0->tv_mode[4] = 0x1000; // turn off 54Mhz upsampling
regs0->g21_reserved[4] = 0x0; // turn off 108Mhz upsampling
tv_setup_TV8202E(1); // setup TV kernel for 9992
#else
tv_setup_TV8202E(0);
#endif // IC_8202E
#ifdef SPHE1000
#ifdef HE1001_TUNER //yarco 20041202
regs0->sft_cfg3 &= 0xffcf; //disable ATAPI
regs0->sft_cfg2 = (regs0->sft_cfg2 & 0xfff1) | 0x06; //select TS interface
#endif
#endif
reset_all_exit();
#if defined(DVB1000_NON_OS) && defined(SUPPORT_USB)
reset_usb();
#endif
}
/**************************************************************************
* Function Name: reset_set_uart0_baudrate *
* Purposes: *
* reset baudrate of uart0 *
* Descriptions: *
* there are 9 type baudrate of uart0 *
* Arguments: None *
* Returns: 0 *
* See also: None *
**************************************************************************/
static inline void reset_set_uart0_baudrate(void)
{
#if defined(F135)
UART0_set_baudrate(BAUDCC(115200, 135000000));
#elif defined(F128_25)
UART0_set_baudrate(BAUDCC(115200, 128250000));
#elif defined(F121_5)
UART0_set_baudrate(BAUDCC(115200, 121500000));
#elif defined(F114_75)
UART0_set_baudrate(BAUDCC(115200, 114750000));
#elif defined(F108)
UART0_set_baudrate(BAUDCC(115200, 108000000));
#elif defined(F101_25)
UART0_set_baudrate(BAUDCC(115200, 101250000));
#elif defined(F94_5)
UART0_set_baudrate(BAUDCC(115200, 94500000));
#elif defined(F87_75)
UART0_set_baudrate(BAUDCC(115200, 87750000));
#elif defined(F81)
UART0_set_baudrate(BAUDCC(115200, 81000000));
#endif
}
/**************************************************************************
* Function Name: reset_change_sysclk *
* Purposes: *
* change system clock *
* Descriptions: *
* there are 19 type of system clock *
* Arguments: None *
* Returns: 0 *
* See also: None *
**************************************************************************/
int
reset_change_sysclk(void)
{
#if defined(F168_75) //wrwu, 2005-01-21, for over-clock
change_system_clock(25);
#elif defined(F162)
change_system_clock(24);
#elif defined(F155_25)
change_system_clock(23);
#elif defined(F148_5)
change_system_clock(22);
#elif defined(F141_75)
change_system_clock(21);
#elif defined(F135)
change_system_clock(20);
#elif defined(F128_25)
change_system_clock(19);
#elif defined(F121_5)
change_system_clock(18);
#elif defined(F114_75)
change_system_clock(17);
#elif defined(F108)
change_system_clock(16);
#elif defined(F101_25)
change_system_clock(15);
#elif defined(F94_5)
change_system_clock(14);
#elif defined(F87_75)
change_system_clock(13);
#elif defined(F81)
change_system_clock(12);
#elif defined(F74_25)
change_system_clock(11);
#elif defined(F67_5)
change_system_clock(10);
#elif defined(F60_75)
change_system_clock(9);
#elif defined(F54)
change_system_clock(8);
#elif defined(F47_25)
change_system_clock(7);
#elif defined(F40_5)
change_system_clock(6);
#elif defined(F33_75)
change_system_clock(5);
#elif defined(F27)
change_system_clock(4);
#elif defined(F13_5)
change_system_clock(2);
#elif defined(F6_75)
change_system_clock(1);
#endif
//reset_set_uart0_baudrate();
return 0;
}
/**************************************************************************
* Function Name: reset_change_sysclk_27M *
* Purposes: *
* change system clock to 27M *
* Descriptions: *
* change system clock *
* Arguments: None *
* Returns: 0 *
* See also: None *
**************************************************************************/
int
reset_change_sysclk_27M(void)
{
change_system_clock(4); UART0_set_baudrate(BAUDCC(115200, 27000000));
// change_system_clock(10); UART0_set_baudrate(BAUDCC(115200, 67500000));
return 0;
}
#ifdef SUPPORT_USB
/**************************************************************************
* Function Name: set_usbpll_reg *
* Purposes: *
* setup regs0->sft_cfg9 *
* Descriptions: *
* setup USB clock *
* Arguments: None *
* Returns: None *
* See also: None *
**************************************************************************/
static inline void set_usbpll_reg(unsigned s, unsigned ns)
{
#ifdef SPHE1000
unsigned cfg7;
cfg7 = regs0->sft_cfg7;
regs0->sft_cfg7 = (cfg7 & ~0xfff) | ((ns<<6)|(s));
#else
unsigned cfg9;
cfg9 = regs0->sft_cfg9;
regs0->sft_cfg9 = (cfg9 & ~0xfff) | ((ns<<6)|(s));
#endif
}
#endif
//
// SYSTEM CLOCK
//
#ifdef SPHE1000
#define LX_F256
static inline void set_lx4189_overclock()
{
// change lx4189 sysclk->270Mhz
volatile UINT32 *ptr=(volatile UINT32*)0xbc010ce0;
BYTE NR=0, NF=0;
BYTE OD=0;
#if defined(LX_F251)
NR=5; NF=93;
#elif defined(LX_F253)
NR=5; NF=94;
#elif defined(LX_F256)
NR=2; NF=38;
#elif defined(LX_F263)
NR=2; NF=39;
#elif defined(LX_F270)
NR=2; NF=40;
#elif defined(LX_F276)
NR=2; NF=41;
#elif defined(LX_F283)
NR=2; NF=42;
#elif defined(LX_F290)
NR=2; NF=43;
#elif defined(LX_F297)
NR=2; NF=44;
#elif defined(LX_F303)
NR=2; NF=45;
#elif defined(LX_F310)
NR=2; NF=46;
#else // F270
NR=2; NF=40;
#endif
regs0->pllc_cfg = (OD<<14)|((NR-2)<<9)|(NF-2);
*ptr = 1;
delay_1us(500);
}
#endif // SPHE1000
/**************************************************************************
* Function Name: set_syspll_reg *
* Purposes: *
* setup regs0->sysclk_div_sel and regs0->sysclk_sel *
* Descriptions: *
* setup system clock *
* Arguments: None *
* Returns: None *
* See also: None *
**************************************************************************/
static inline void set_syspll_reg(unsigned a, unsigned b)
{
int i;
#ifdef SPHE1000
regs0->sysclk_div_sel= 0x0404; // slow it down
regs0->sysclk_sel=((a)|(10<<4));
for (i=0;i<1000 && (regs0->sysclk_sel&((1<<8)|(1<<11)|(1<<12))); i++) ;
regs0->sysclk_div_sel= ((b)|(0<<8));
#if 0
set_lx4189_overclock();
#endif
#else
regs0->sysclk_div_sel= 4; // slow it down
regs0->sysclk_sel=a;
for (i=0;i<1000 && (regs0->sysclk_sel&((1<<11)|(1<<12))); i++) ;
#ifdef CLK54_USE_USBPLL
b |= (2<<6); // CLK54 select USB OSCx2
//b |= (3<<6); // CLK54 select USB OSC
#endif
regs0->sysclk_div_sel= b;
#endif
}
/**************************************************************************
* Function Name: reset_delayX *
* Purposes: delay time *
* Descriptions: delay time *
* Arguments: None *
* Returns: None *
* See also: None *
**************************************************************************/
static void reset_delayX(int n)
{
while (n-->0) {
asm volatile ("nop");
}
}
#define CLKUV(u,v) (((u)<<4)|(v))
#define CLKUV_U(uv) ((uv)>>4)
#define CLKUV_V(uv) ((uv)&0x0f)
static const UINT8 sysclk_table[26] = //wrwu, 2005-01-21, for over-clock
{
CLKUV(1,0), // 00: -----
CLKUV(1,4), // 01: 0.25x 6.75
CLKUV(1,3), // 02: 0.50x 13.5
CLKUV(9,3), // 03: 0.75x 20.25
CLKUV(1,2), // 04: 1.00x 27
CLKUV(5,2), // 05: 1.25x 33.75
CLKUV(9,2), // 06: 1.50x 40.5
CLKUV(13,2), // 07: 1.75x 47.25
CLKUV(1,1), // 08: 2.00x 54
CLKUV(3,2), // 09: 2.25x 60.75
CLKUV(5,1), // 10: 2.50x 67.5
CLKUV(7,1), // 11: 2.75x 74.25
CLKUV(9,1), // 12: 3.00x 81
CLKUV(11,1), // 13: 3.25x 87.75
CLKUV(13,1), // 14: 3.50x 94.5
CLKUV(0,1), // 15: 3.75x 101.25
CLKUV(1,0), // 16: 4.00x 108 xx
CLKUV(2,1), // 17: 4.25x 114.75
CLKUV(3,1), // 18: 4.50x 121.50
CLKUV(4,0), // 19: 4.75x 128.25 xx
CLKUV(5,0), // 20: 5.00x 135
CLKUV(6,0), // 21: 5.25x 141.75
CLKUV(7,0), // 22: 5.50x 148.5
CLKUV(8,0), // 23: 5.75x 155.25
CLKUV(9,0), // 24: 6.00x 162
CLKUV(10,0), // 25: 6.25x 168.75
#if 0
CLKUV(11,0), // 26: 6.50x 175.5
CLKUV(12,0), // 27: 6.75x 181.25
CLKUV(13,0), // 28: 7.00x 189
#endif
};
static const UINT8 baudrate_table[26] = { //wrwu, 2005-01-21, for over-clock
BAUDCC(115200,6750000*0),
BAUDCC(115200,6750000*1),
BAUDCC(115200,6750000*2),
BAUDCC(115200,6750000*3),
BAUDCC(115200,6750000*4),
BAUDCC(115200,6750000*5),
BAUDCC(115200,6750000*6),
BAUDCC(115200,6750000*7),
BAUDCC(115200,6750000*8),
BAUDCC(115200,6750000*9),
BAUDCC(115200,6750000*10),
BAUDCC(115200,6750000*11),
BAUDCC(115200,6750000*12),
BAUDCC(115200,6750000*13),
BAUDCC(115200,6750000*14),
BAUDCC(115200,6750000*15),
BAUDCC(115200,6750000*16),
BAUDCC(115200,6750000*17),
BAUDCC(115200,6750000*18),
BAUDCC(115200,6750000*19),
BAUDCC(115200,6750000*20),
BAUDCC(115200,6750000*21),
BAUDCC(115200,6750000*22),
BAUDCC(115200,6750000*23),
BAUDCC(115200,6750000*24),
BAUDCC(115200,6750000*25)
};
#ifdef SHOW_SYSTEM_CLOCK//nono 4-4-6 0:29
int get_sysclk;
#endif//SHOW_SYSTEM_CLOCK
/**************************************************************************
* Function Name: change_system_clock *
* Purposes: *
* 1. disable interrupt *
* 2. get idx *
* 3. set syspll *
* 4. set sdram-timing *
* 5. restore interrupt setting *
* Descriptions: *
* change system clock *
* Arguments: None *
* Returns: 0 *
* See also: None *
**************************************************************************/
int
change_system_clock(int uvidx)
{
unsigned uv, u, v, IEc;
#ifdef SHOW_SYSTEM_CLOCK//nono 4-4-6 0:29
//get get_sysclk;print on cus_menu
get_sysclk = uvidx;
#endif//#ifdef SHOW_SYSTEM_CLOCK
// disable interrupt
IEc = cpu_intr_disable();
//
reset_delayX(100);
// get idx
uv = sysclk_table[uvidx];
u = CLKUV_U(uv);
v = CLKUV_V(uv);
#if defined(BOOT_HALF) || defined(IC_8202E)
if (v!=0) v--;
#endif
// set syspll
set_syspll_reg(u,v);
#ifdef SUPPORT_USB
//set_usbpll_reg(0x12,0x1b); // 96mhz/48mhz
//set_usbpll_reg(0x1b,0x1b); // 54mhz/27mhz
//regs0->sft_cfg7 |= (0xf<<8); // clk27 select clk54/2
//regs0->sft_cfg7 |= (3<<12); // output clk54 to pin 65
#endif
// set sdram-timing
if (uvidx<10)
set_sdram_timing_low();
else
set_sdram_timing();
// restore interrupt setting
cpu_intr_config(IEc);
#if !defined(SPHE8202) && !defined(SPHE1000)
// initialize stc-divisor
regs0->stc_divisor = uvidx*75-1;
UART0_set_baudrate(baudrate_table[uvidx]);
#endif
return 0;
}
/**************************************************************************
* Function Name: slowdown_test *
* Purposes: *
* Descriptions: *
* Arguments: None *
* Returns: None *
* See also: None *
**************************************************************************/
#if 0
void
slowdown_test(void)
{
reset_change_sysclk_27M();
UART0_set_baudrate(BAUDCC(115200, 27000000));
delay_1ms(200);
reset_change_sysclk();
UART0_set_baudrate(BAUDCC(115200, 121500000));
}
#endif
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