📄 reset.c
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#endif
/**************************************************************************
* Function Name: reset_all *
* Purposes: *
* 1. DISABLE INTR *
* 2. REGF + ROMIF setup *
* 3. EMUIO/UART setup (interrupt not yet enabled) *
* 4. APLL setup (before GPIO for correct XCK) *
* 5. GPIO setup *
* 6. SDRAM size setup *
* 7. TIMER setup *
* 8. SDRAM memory mapping configuration *
* 9. VIDDEC *
* 10. SUP *
* 11. MULTI-TASK *
* 12. ENABLE INTR *
* 13. IOP include IR 、VFD、TV-encoder、DAC *
* Descriptions: *
* reset all, including some interface. *
* Arguments: None *
* Returns: None *
* See also: None *
**************************************************************************/
void reset_all(void)
{
#ifdef SPHE8202 // longson 2004.02.16
regs0->sft_cfg4 = 0x6073; // disable SC1_OUT and TRAY_OUT
regs0->gpio_oe[0] = 0x0c; // enable GPIO[2] and GPIO[3] output
#endif
//
// at this time only reset.c/crt0.S/lexra.S/sysmain.c are assumed to
// be in memory
//
//
// load code to sdram if required
//
#ifdef SPHE1000
#if defined(LOAD_OTHER) || defined(ROM_SDRAM_SHARE_BUS)
LoadModual(MODUAL_OTHER); write_stamp(STAMP_LOAD_MODULE_OTHER);
#endif
msg_init();
#endif
//
// prolog
reset_all_enter();
//
// reset basic system (again)
reset_system();
write_stamp(STAMP_RESET_SYSTEM);
#ifndef START_NO_VPP_DELAY //linrc add for nintaus 2004-7-12 19:51
reset_tvdac();
#endif
#ifdef POWER_ON_VIDEO_DAC_OFF
tv_dacoff( (0x01<<0)|(0x01<<1)|(0x01<<2)|(0x01<<3)|(0x01<<4)|(0x01<<5) );
#endif//POWER_ON_VIDEO_DAC_OFF
//
// change system clock from 108MHz to required frequency
#ifndef USE_DEFAULT_CLOCK //2004/10/21 wjzhang , sphe1000B(stb-dvd): use default clock
#ifdef SPHE1000
{
UINT32 CFG_board_config = regs0->hw_cfg;
if (CFG_board_config == 9) regs0->sft_cfg2 |= (3<<14);
reset_change_sysclk(); write_stamp(STAMP_CHANGE_SYSCLK);
if (CFG_board_config == 9) regs0->sft_cfg2 &= ~(3<<14);
}
#else
reset_change_sysclk(); write_stamp(STAMP_CHANGE_SYSCLK);
#endif
#endif
//
// load code to sdram if required
//
#ifndef SPHE1000
#if defined(LOAD_OTHER) || defined(ROM_SDRAM_SHARE_BUS)
LoadModual(MODUAL_OTHER); write_stamp(STAMP_LOAD_MODULE_OTHER);
#endif
#endif
#ifdef TCL_STANDBY
regs0->sft_cfg1 &= ~(0x1 << 3);//gpio 3 enable
regs0->gpio_master[ 3/16 ] |= 0x1 << (3%16);//gpio 3 for mips
regs0->gpio_oe[ 3/16 ] |= 0x1 << (3%16);//output
regs0->gpio_out[3/16 ] |= (0x1 << (3%16));
//delay_1ms(500);
regs0->gpio_master[ 2/16 ] |= 0x1 << (2%16);//gpio 2 for mips
regs0->gpio_oe[ 2/16 ] &= ~(0x1 << (2%16));//input
//delay_1ms(500);
#endif
LoadModual(MODUAL_AP); write_stamp(STAMP_LOAD_MODULE_AP);
LoadModual(MODUAL_FREE); write_stamp(STAMP_LOAD_MODULE_FREE);
LoadModual(MODUAL_CDROM); write_stamp(STAMP_LOAD_MODULE_CDROM);
//
// at this time all essential code is decompressed and loaded.
// OTHER/AP/FREE/CDROM code are loaded
//
//
// blank display
disable_video();
write_stamp(STAMP_DISABLE_VIDEO);
#ifdef SUPPORT_AUDIO_RESET
GpioResetAudio();
#endif
//720 generate DAC clock first, Jeff 20020712
#ifndef DVD728
// setup audio clockgen (to correct format and XCK)
hwsetup_audio_clkgen_init();
#endif
#ifdef SUPPORT_EPP
// reset emuio fifo
reset_io();
#endif
#ifdef SPHE8202
// UART0_set_baudrate(BAUDCC(115200, 135000000));
// UART0_set_baudrate(BAUDCC(115200, 128250000));
// UART0_set_baudrate(BAUDCC(115200, 121500000));
// UART0_set_baudrate(BAUDCC(115200, 114750000));
// UART0_set_baudrate(BAUDCC(115200, 108000000));
#endif
#ifdef SUPPORT_UART_COMMAND //kenny support uart to communicate with external MCU
reset_uart();
#endif
#if defined(DVDRELEASE) && !defined(SPHE1000)
#if defined(QSI_SHOW_ERR_RATE)
UART0_set_baudrate(BAUDCC(115200, 121500000));
psprintf(linebuf,"------------Release UART------------\n");
UART0_puts(linebuf);
#elif defined(UART_WITHOUT_DEBUG_MODE)//axel 2004/10/19 for the communication with external MCU
UART0_set_baudrate(BAUDCC(9600, 121500000));
//psprintf(linebuf,"------------Release UART------------\n");
//UART0_puts(linebuf);
#else
extern void sft_hvsync();//4-4-6 0:43
//sft_hvsync(1);
sft_hvsync(); //freyman 2004-2-27 12:01
#endif
#endif
#ifdef UART_SWAP //axel swap uart0 and uar1 2004/10/29
UART1_set_baudrate(BAUDCC(115200, 121500000));
psprintf(linebuf,"------------Release UART------------\n");
UART1_puts(linebuf);
#endif
#if 0
regs0->sft_cfg2 |= 1<<15;
UART0_set_baudrate(BAUDCC(115200, 121500000));
UART1_set_baudrate(BAUDCC(115200, 121500000));
UART0_puts("enable UART0\n");
UART1_puts("enable UART1\n");
#endif
//
// Enable UART interrupt here (to enable emuio access)
reset_all_enable_intr_only_uart(); write_stamp(STAMP_ENABLE_INTR_0);
#if defined(SPHE8202)//nono
#ifdef MP_BOARD_256_PIN_NON_SHARE
gpGPIOini = 0xff;
#else
gpGPIOini = 0;
#endif
#endif//SPHE8202
//
// hardware initialization
#ifdef SPHE1000
reset_gpio_1000();
#else
reset_gpio(); // setup GPIO directions
#endif
#if 0//def SUPPORT_UART_COMMAND //inform external MCU Power is ok and releas vfd and ir
Inform_MCUOK();
#endif
#ifdef SYS_TEST_REG_00
sys_test_reg_00=0x7;
#endif
#ifdef SUPPORT_POWER_STB //jinping for power standby 2002-7-6 17:56
POWER_STB_SET( STANDBY ); // power on;
#endif
#ifdef SUPPORT_AMP // for SVA DVD solution
AMP_MUTE_SET(1); // tripth amp. high mute; mute amp.
amp_onoff_flag = 0;//default is 0. 0:amp off,out to TV; 1:amp on, out to amp
#endif
//
// Load other code modules
LoadModual(MODUAL_MPEG); write_stamp(STAMP_LOAD_MODULE_MPEG);
LoadModual(MODUAL_AP2); write_stamp(STAMP_LOAD_MODULE_AP2);
//
// setup framebuffer/memory initial configuration
enable_portable_bonding(0);
#ifdef PORTABLE_DVD//jhuang 2003/12/3
memory_config_saved = IOP_CONFIG_PDVD;
is_iop_ready();
#endif
memory_config_saved = 0xff;
config_memory(MEMORY_DVD_NTSC);
write_stamp(STAMP_CONFIG_MEMORY);
//
// setup timer
init_timer();
//
// initialize audio/video/sup decoder
// init_audio(); //terry mark it on 2002/2/24 02:40PM ,avoid A/D to be turned on at startup
init_video_decoder();
init_sup();
pe_init();
//
// Abort previous decoding tasks
MacroAbort();
//
// Reset interrupt routines
// atapi: (not used now)
// task: task-switching
reset_atapi_intr();
#ifndef DVDRELEASE
reset_task();
#endif
//
// Reset watchdog
watchdog_renew(0xffff); // n*16/90k, first time we set to maximum (about 12-second)
watchdog_onoff(1);
write_stamp(STAMP_RESET_WATCHDOG);
//
// Enable all used interrupts
reset_all_enable_intr_all(); write_stamp(STAMP_ENABLE_INTR_1);
//
// Initialize OSD (before enable TV-encoder)
reset_osd(); write_stamp(STAMP_RESET_OSD);
//
// basic service on
// interrupt has been on
//
//
// IOP IOP IOP IOP IOP IOP
//
// setup iop
reset_status_puts("setup iop.\n");
reset_iop();
// iop service #1
reset_status_puts("setup ir inf.\n");
reset_ir();
// iop service #2
#if defined(SUPPORT_VFD)&&defined(SUPPORT_VFD_PANEL) //lijd 2004-12-4 11:39
reset_status_puts("setup vfd inf.\n");
reset_vfd();
#endif
#if defined(GPIO_KEY_LIGHT)
init_keylight_io();
#endif
// iop service #3 (if 721/725)
reset_status_puts("setup tv inf.\n");
#ifdef DVD728
#define NO_SYNC_ON_G
#ifdef NO_SYNC_ON_G
setup_sync_on_G(0); // support SCART TV, no sync signal on G channel
#endif
setup_display(0,1); // FIX: this is for osd/tv-encoder to keep coherent.
// delay_1ms(200); //terry,2003/8/11 11:44AM
/*
#ifdef BBK_DVD//zhaoyanhua add 2003-11-24 14:23
tv_init_output();
#endif
*/
#else
tv_setup();
#endif
#ifdef DIGITAL_VIDEO_OUT
#ifdef SPHE8202
#ifdef MP_BOARD_256_PIN_NON_SHARE
#ifdef CCIR656_TYPE1
regs0->sdc_data_cnt[6][0] |= (0x0e);//Disable ROM_A20(Pin225),ROM_A21(Pin226),ROM_A22(Pin227) as GPIO92,93,94
regs0->sdc_data_cnt[6][0] |= (0x1 <<4); //CCIR656 ENABLE on Pin225~233
#elif defined(CCIR656_TYPE2)
regs0->sft_cfg7 |= (0x1 << 4); //rbhung Only for TEST
regs0->sft_cfg3 &= ~(0x1 << 5); //Disable AUD4 as GPIO50 for TV_CLK ,pin 193
#endif
#endif //MP_BOARD_256_PIN_NON_SHARE
#else //8210
regs0->sft_cfg6 |= (0x1 << 14); //CCIR656 ENABLE
regs0->sft_cfg3 |= (0x7 << 9); //CCIR SYNC FROM PIN185,186
regs0->sft_cfg2 &= ~(0xf << 5); //UART1 SELECT
//regs0->osd_tv_out |=(0x1 << 1); //Cb\Cr SWAP
regs0->osd_tv_out |=(0x1 << 3); //CCIR EDGE SELECT
//regs0->sft_cfg2 |= (0x7 << 9); //TV_LCD RGB ENABLE
//regs0->ri_misc_b0 |= (0x3<<11); //VIDEO CLK SELECT
#endif
#endif
// iop service #4
#ifdef SETUP_DAC
reset_status_puts("setup dac.\n");
dac_setup();
#endif
// iop service #5
#if defined(PT2322)||defined(PT2320)
reset_status_puts("setup pt2322.\n");
init_pt_audio();
#endif
#if defined(TAS3001_AMP)||defined(NO_AMP_ONLY_TUNER) //use TI 3001 amplifier 2-8-22 12:58
{
// extern int AudioIOControl(UINT16 wCode, BYTE cType, UINT16 wParam); //kenny mark it
// AudioIOControl(2, 15, 0); //set 720 pcm volume 2==VOLUME,15=max volume
regs0->gpio_sel |= GPIOSEL_10_GPIOS; //use gpio22,23 communicate with MCU// jason 2-11-4 19:05
regs0->gpio_out[23/16]&=(~(3<<(22%16)));
regs0->gpio_oe[23/16] |=(3<<(22%16));
#ifndef NO_AMP_ONLY_TUNER
tas3001_reset();
#endif
}
#endif
#if defined(TAS5026_AMP) //use TI 3001 amplifier 2-8-22 12:58
{
// extern int AudioIOControl(UINT16 wCode, BYTE cType, UINT16 wParam); //kenny mark it
// AudioIOControl(2, 15, 0); //set 720 pcm volume 2==VOLUME,15=max volume
tas5026_reset();
}
#endif
// setup dsp port
{
int i;
for (i=0;i<16;i++) regs0->dsp24_port[i] = 0; //Jeff 20011029
}
#ifdef SETUP_UART1
// enable UART1
{
UINT32 u;
// setup baudrate
UART1_set_baudrate(UART_BAUD_57600);
// change pinmux
u = regs0->sft_cfg2;
u = (u & ~(0x0f<<5)) | (0x09<<5);
regs0->sft_cfg2 = u;
while (1) UART1_puts("test uart #1\n");
}
#endif
/*
// servo testing code
#ifdef DVD_SERVO
#ifndef SOFT_ATAPI //DVD_SERVO
ServoDecInit(); // barry add for init servo
ResetInterfaceProc();
#endif
regs0->emu_cfg[16] = 0x00; // ROM-pattern disable
regs0->rf_servo_band_en = 0x00; //
#endif
*/
#ifdef VOLUME_RECODE //gerry add it before init audio,2004-7-6 9:36
volume_init();
#endif//VOLUME_RECODE
//
// initialize audio, put it here to avoid CS4334 noise
AUDIF_Init_Audio();//2004AUDDRV init_audio();
//
// ???
#ifdef CS8403_ENABLE
#ifdef SPHE8202
init_cs8403a__();
#else
regs0->gpio_master[55 / 16] |= (0x1 << (55 % 16)); //pin155, GPIO[55]
regs0->gpio_oe[55 / 16] |= (0x1 << (55 % 16));
regs0->gpio_out[55 / 16] |= (0x1 << (55 % 16));
init_cs8403a__();
#endif
#endif
#ifdef PCM1742 //Jeff 20030917
dac_turn_on();
#endif
#ifdef CS4360 //huziqin
//printf("config 4360\n");
config_cs4360();
#endif
// VPP Pixel Aspect Ratio
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