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📄 regmap_8202.h

📁 Sunplus 8202S source code.
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  UINT32 g25_reserved_0[2];                     // 03  803~ 804 (0c8c)
  UINT32 invq_vol_header;                       // 05  805      (0c94)
  UINT32 g25_reserved_1[26];                    // 06  806~ 831 (0c98)

  // GROUP 26: RI/ROM
  UINT32 rom_config;                            // 00  832      (0d00) $bffe8d00
  UINT32 wait_cyc1_0;                           // 01  833      (0d04)
  UINT32 wait_cyc3_2;                           // 02  834      (0d08)
  UINT32 oe_wait_cyc1_0;                        // 03  835      (0d0c)
  UINT32 oe_wait_cyc3_2;                        // 04  836      (0d10)
  UINT32 we_wait_cyc1_0;                        // 05  837      (0d14)
  UINT32 we_wait_cyc3_2;                        // 06  838      (0d18)
  UINT32 iochrdy_wait_cyc;                      // 07  839      (0d1c)
  UINT32 rom1_base;                             // 08  840      (0d20)
  UINT32 rom2_base;                             // 09  841      (0d24)
  UINT32 rom3_base;                             // 0a  842      (0d28)
  UINT32 pcmcia_iorw_wait;                      // 0b  843      (0d2c)
  UINT32 pcmcia_ctrl;                           // 0c  844      (0d30)
  UINT32 g26_reserved1[8];                      // 0d  845~ 852 (0d34)
  UINT32 adt[4];                                // 15  853~ 856 (0d54)
  UINT32 dat[4];                                // 19  857~ 860 (0d64)
  UINT32 adm[2];                                // 1d  861~ 862 (0d74)
  UINT32 dar;                                   // 1f  863      (0d7c)

  // GROUP 27: System Bus Arbitrator
  UINT32 sbar_config;                           // 00  864      (0d80) $bffe8d80
  UINT32 sbar_prr[16];                          // 01  865~ 880 (0d84)
  UINT32 g27_reserved[2];                       // 11  881~ 882 (0dc4)
  UINT32 sbar_sdram_rom;                        // 13  883      (0dcc)
  UINT32 g27_reserved1[12];                     // 14  884~ 895 (0dd0)

  // GROUP 28: Bridge
  UINT32 rf_sdramif_tbya;                       // 00  896      (0e00) $bffe8e00
  UINT32 rf_servo_band_en;                      // 01  897      (0e04)
  UINT32 rf_servo_band_val;                     // 02  898      (0e08)
  UINT32 g28_reserved[29];                      // 03  899~ 927 (0e0c)

  // GROUP 29: Servo
  UINT32 rf_regif_addr;                         // 00  928      (0e80) $bffe8e80
  UINT32 rf_regif_wdata;                        // 01  929      (0e84)
  UINT32 rf_regif_rdata;                        // 02  930      (0e88)
  UINT32 rf_regif_sample_ctrl;                  // 03  931      (0e8c)
  UINT32 rf_regif_intr_addr;                    // 04  932      (0e90)
  UINT32 rf_regif_intr_wdata;                   // 05  933      (0e94)
  UINT32 rf_regif_intr_rdata;                   // 06  934      (0e98)
  UINT32 g29_reserved[25];                      // 07  935~ 959 (0e9c)

  // GROUP 30: Emulation control
  UINT32 emu_cfg[32];                           // 00  960~ 991 (0f00) $bffe8f00

  // GROUP 31: Audio hardware control
  UINT32 aud_reset;                             // 00  992      (0f80) $bffe8f80
  UINT32 aud_pcm_cfg;                           // 01  993      (0f84)
  UINT32 aud_spdif_cfg;                         // 02  994      (0f88)
  UINT32 aud_enable;                            // 03  995      (0f8c)
  UINT32 aud_adc_stereo_cfg;                    // 04  996      (0f90)
  UINT32 aud_adc_mono_cfg;                      // 05  997      (0f94)
  UINT32 aud_pcm_ramp_delta;                    // 06  998      (0f98)
  UINT32 aud_pcm_ramp_cfg;                      // 07  999      (0f9c)
  UINT32 aud_pcm_ramp_value;                    // 08 1000      (0fa0)
  UINT32 aud_spdif_period;                      // 09 1001      (0fa4)
  UINT32 aud_fifo_flag;                         // 0a 1002      (0fa8)
  UINT32 aud_chn_pcm_cnt[10];                   // 0b 1003~1012 (0fac)
  UINT32 aud_xck_cfg;                           // 15 1013      (0fd4)
  UINT32 aud_pcm_bck_cfg;                       // 16 1014      (0fd8)
  UINT32 aud_iec_bclk_cfg;                      // 17 1015      (0fdc)
  UINT32 aud_adc_mclk_cfg;                      // 18 1016      (0fe0)
  UINT32 aud_dsp_run_cnt;                       // 19 1017      (0fe4)
  UINT32 aud_dsp_stall_cnt;                     // 1a 1018      (0fe8)
  UINT32 aud_dsp_reset_flag;                    // 1b 1019      (0fec)
  UINT32 aud_dsp_dec_cnt_toggle;                // 1c 1020      (0ff0)
  UINT32 aud_dsp_dec_cnt;                       // 1d 1021      (0ff4)
  UINT32 aud_fpga_v2[2];                        // 1e 1022~1023 (0ff8)

  // GROUP 32
  //UINT32 g32_reserved[32];                    // 00 1024~1055 (1000) $bffe9000
  UINT32 card_mediaType;
  UINT32 g32_reserved1[10];
  UINT32 fm_gpio_mode; // 11
  UINT32 fm_gpio_len;	//12
  UINT32 g32_reserved2[19];

  // GROUP 33
  //UINT32 g33_reserved[32];                      // 00 1056~1087 (1080) $bffe9080
  UINT32 ndData;             // 0x20
  UINT32 ndTimeProf;         // 0x21
  UINT32 g33_reserved1;      // 0x22
  UINT32 ndCtrl[2];          // 0x23 ~ 0x24
  UINT32 g33_reserved2[11];  // 0x25 ~ 0x2f
  UINT32 ataData;            // 0x30
  UINT32 cfCtrl;             // 0x31
  UINT32 cfAddrLsb;          // 0x32
  UINT32 cfAddrMsb;          // 0x33
  UINT32 ataMode;            // 0x34
  UINT32 ataPulsWidth;       // 0x35
  UINT32 ataCsnn;            // 0x36
  UINT32 g33_reserved3[2];   // 0x37 ~ 0x38
  UINT32 ataRegnn;           // 0x39
  UINT32 ataRstnn;           // 0x3A
  UINT32 fmGpioA;            // 0x3B
  UINT32 g33_reserved4;      // 0x3C
  UINT32 cfActTime;          // 0x3D
  UINT32 g33_reserved5[2];   // 0x3e ~ 0x3f

  // GROUP 34
  //UINT32 g34_reserved[32];                      // 00 1088~1119 (1100) $bffe9100
    UINT32  g34_reserved1[6]; 					   // (1100) $bffe9100
	UINT32  spiFreq;            /* 0x46          */// (1106) $bffe9118
	UINT32  spiConfig;          /* 0x47          */// (1107) $bffe911C
	UINT32  spiMode;            /* 0x48          */
	UINT32  g34_reserved2[2];
	UINT32  spiStatus;          /* 0x4B          */
	UINT32  g34_reserved3[4];   /* 0x4C ~ 0x4F   */
	UINT32  sdRst;              /* 0x50          */
	UINT32  sdConfig;           /* 0x51          */
	UINT32  sdCtrl;             /* 0x52          */
	UINT32  sdStatus0;          /* 0x53          */
	UINT32  sdStatus1;          /* 0x54          */
	UINT32  sdBlockSize;        /* 0x55          */
	UINT32  g34_reserved4;      /* 0x56          */
	UINT32  sdRspTmr;           /* 0x57          */
	UINT32  sdCrcTmr;           /* 0x58          */
	UINT32  sdPioDataTx;        /* 0x59          */
	UINT32  sdPioDataRx;        /* 0x5a          */
	UINT32  sdCmdBuf[5];        /* 0x5b ~ 0x5f   */
  // GROUP 35
  //UINT32 g35_reserved[32];                      // 00 1120~1151 (1180) $bffe9180
    UINT32  sdRspBuf[6];        /* 0x60 ~ 0x65   */
	UINT32  sdCrc7Buf;          /* 0x66          */
	UINT32  sdCrc16Buf0Lsb;     /* 0x67          */
	UINT32  sdCrc16Buf0Msb;     /* 0x68          */
	UINT32  sdCrc16Buf1Lsb;     /* 0x69          */
	UINT32  sdCrc16Buf1Msb;     /* 0x6a          */
	UINT32  sdCrc16Buf2Lsb;     /* 0x6b          */
	UINT32  sdCrc16Buf2Msb;     /* 0x6c          */
	UINT32  sdCrc16Buf3Lsb;     /* 0x6d          */
	UINT32  sdCrc16Buf3Msb;     /* 0x6e          */
	UINT32  sdCrc16Flag;        /* 0x6f          */

    UINT32  msPioDmaRst;        /* 0x70          */
    UINT32  msCmd;              /* 0x71          */
    UINT32  g35_reserved1[2];   /* 0x72,0x73     */
    UINT32  msModeSpeed;        /* 0x74          */
    UINT32  msTimout;           /* 0x75          */
    UINT32  msState1;           /* 0x76          */
    UINT32  msState2;           /* 0x77          */
    UINT32  msRddata[4];        /* 0x78~0x7B     */
    UINT32  msCrcBufLsb;        /* 0x7C          */
    UINT32  msCrcBufMsb;        /* 0x7D          */
    UINT32  msCrcError;         /* 0x7E          */
    UINT32  msPioRdy;           /* 0x7F          */


    // GROUP 36

    UINT32  msWdData[16];       /* 0x80~0x8f     */
    UINT32  g36_reserved1[16];

    // GROUP 37
    //UINT32 g37_reserved[32];                      // 00 1184~1215 (1280) $bffe9280
    UINT32  eccReset;           /* 0xa0        */
    UINT32 	psFmData;           /* 0xa1        */
    UINT32 	eccMask;            /* 0xa2        */
    UINT32 	eccMode;            /* 0xa3        */
    UINT32  ecc1;               /* 0xa4        */
    UINT32 	ecc0;               /* 0xa5        */
    UINT32 	ecc2;               /* 0xa6        */
    UINT32 	ecc4;               /* 0xa7        */
    UINT32 	ecc3;               /* 0xa8        */
    UINT32  ecc5;               /* 0xa9        */
    UINT32 	ecc7;               /* 0xaa        */
    UINT32 	ecc6;               /* 0xab        */
    UINT32 	ecc8;               /* 0xac        */
    UINT32 	ecca;               /* 0xad        */
    UINT32 	ecc9;               /* 0xae        */
    UINT32 	eccb;               /* 0xaf        */
    UINT32  g37_reserved1[16];  /* 0xb0~ 0xbf  */

  // GROUP 38
  UINT32 g38_reserved[32];                      // 00 1216~1247 (1300) $bffe9300

  // GROUP 39
  UINT32 gpio_mode_B;
  UINT32 g39_reserved[31];                      // 00 1248~1279 (1380) $bffe9380

  // GROUP 40: DMA Controller Register
  UINT32 dma_data;                              // 0x00 1280      (1400) $bffe9400
  UINT32 dma_srcDst;                            // 0x01 1281~1308
  UINT32 dma_size;                              // 0x02
  UINT32 g40_reserved1;    						// 0x03
  UINT32 dma_ctrl;								// 0x04
  UINT32 dma_base_addrL;   						// 0x05
  UINT32 dma_base_addrH;						// 0x06
  UINT32 g40_reserved2[14];						// 0x07 ~  0x14
  UINT32 dma_start; 							// 0x15
  UINT32 g40_reserved3; 						// 0x16
  UINT32 dma_cmp;								// 0x17
  UINT32 dma_cmpEn;								// 0x18
  UINT32 g40_reserved4[7];   					// 0x19 ~  0x1f

  // GROUP 41: (EMU) SDRAM 6A
  UINT32 sdc_data_cnt[14][2];                   // 00 1312~1339 (0520) $bffe9480
  UINT32 sdc_n_req_cnt[2];                      // 1c 1340~1341 (14f0)
  UINT32 sdc_cke_cnt[2];                        // 1e 1342~1343 (14f8)

  // GROUP 42~44
  UINT32 g42_reserved[32];                      // 00 1344~1375 (1500) $bffe9500
  UINT32 g43_reserved[32];                      // 00 1376~1407 (1580) $bffe9580
  UINT32 g44_reserved[32];                      // 00 1408~1439 (1600) $bffe9600

  // GROUP 45:  GAME16  
  UINT32 game16_control;				// 00  512~ 543 (0800) $bffe9680
  UINT32 game16_status;				// 0xbffe8804
  UINT32 game16_code_base;				// 0xbffe8808
  UINT32 game16_vram_base;				// 0xbffe880c
  UINT32 game16_work_base; 			// 0xbffe8810
  UINT32 game16_game_dsp_dec_base;				// 0xbffe8814
  UINT32 game16_frame_base0;			// 0xbffe8818				
  UINT32 game16_frame_base1;			// 0xbffe881c
  UINT32 game16_version;				// 0xbffe8820
  UINT32 game16_int_mode;				// 0xbffe8824
  UINT32 game16_io_data1;				// 0xbffe8828
  UINT32 game16_io_data2;				// 0xbffe882c						
  UINT32 game16_io_data3;				// 0xbffe8830		
  UINT32 game16_dma_control;			// 0xbffe8834			
  UINT32 game16_game_dsp_dec_control;			// 0xbffe8838		
  UINT32 game16_game_dsp_dec_wait;				// 0xbffe883c			
  UINT32 game16_game_dsp_dec_buf_base;			// 0xbffe8840	
  UINT32 game16_game_dsp_dec_buf_size;			// 0xbffe8844
  UINT32 game16_game_dsp_dec_buf_in;			// 0xbffe8848 
  UINT32 game16_game_dsp_dec_buf_out;			// 0xbffe884c
  UINT32 game16_game_dsp_dec_ice_base;			// 0xbffe8850
  UINT32 game16_game_dsp_dec_int_addr;			// 0xbffe8854  
  UINT32 game16_disp_control;			// 0xbffe8858  
  UINT32 game16_risc_control;			// 0xbffe885c 
  UINT32 game16_risc_data;				// 0xbffe8860   
  UINT32 g45_reserved[7];			// 

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