📄 regmapa_8200.h
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#define RF_DMA_DONE 4*357
#define RF_G11_RESERVED_26 4*358
#define RF_G12_DVDDSP_VY 4*384
#define RF_G12_DVDDSP_VX 4*385
#define RF_DVDDSP_FUNCTION 4*386
#define RF_DVDDSP_ATA_CONFIG 4*387
#define RF_DVDDSP_BLOCKSIZE 4*388
#define RF_DVDDSP_BLOCKLENGTH 4*389
#define RF_G12_DVDDSP_RY 4*390
#define RF_DVDDSP_RX 4*391
#define RF_DVDDSP_PUBLIC 4*392
#define RF_DVDDSP_UDE_CONFIG 4*393
#define RF_DVDDSP_ATA_PIO_CYCLE 4*394
#define RF_DVDDSP_ATA_UDMA_CYCLE 4*395
#define RF_G12_RESERVED_4 4*396
#define RF_DVDDSP_MON_4 4*400
#define RF_G12_RESERVED1_12 4*404
#define RF_CSS_TK0 4*416
#define RF_CSS_TK1 4*417
#define RF_CSS_TK2 4*418
#define RF_CSS_TK3 4*419
#define RF_CSS_TBYTE 4*420
#define RF_CSS_PUBLIC 4*421
#define RF_CSS_CONFIG 4*422
#define RF_CSS_L0 4*423
#define RF_CSS_L1 4*424
#define RF_CSS_R0 4*425
#define RF_CSS_R1 4*426
#define RF_CPPM_AUKEY3 4*427
#define RF_CPPM_AUKEY2 4*428
#define RF_CPPM_AUKEY1 4*429
#define RF_CPPM_AUKEY0 4*430
#define RF_G13_RESERVED_17 4*431
#define RF_IOP_CONTROL 4*448
#define RF_IOP_STATUS 4*449
#define RF_IOP_BP 4*450
#define RF_IOP_REGSEL 4*451
#define RF_IOP_REGOUT 4*452
#define RF_IOP_MEMLIMIT 4*453
#define RF_G14_RESERVED_2 4*454
#define RF_IOP_DATA_8 4*456
#define RF_G14_RESERVED1_16 4*464
#define RF_SUP_FST_CMD_ADDR 4*480
#define RF_SUP_SND_CMD_ADDR 4*481
#define RF_SUP_H_SIZE 4*482
#define RF_SUP_MODE 4*483
#define RF_SUP_TV_MODE 4*484
#define RF_SUP_PANNING 4*485
#define RF_SUP_ASPECT_RATIO 4*486
#define RF_SUP_MON_5 4*487
#define RF_SUP_CONFIG 4*492
#define RF_SUP_BUFFER_LIMIT 4*493
#define RF_G15_RESERVED_18 4*494
#define RF_G16_RESERVED_32 4*512
#define RF_G17_RESERVED_32 4*544
#define RF_UART0_DATA 4*576
#define RF_UART0_LSR 4*577
#define RF_UART0_MSR 4*578
#define RF_UART0_LCR 4*579
#define RF_UART0_MCR 4*580
#define RF_UART0_DIV_L 4*581
#define RF_UART0_DIV_H 4*582
#define RF_UART0_ISC 4*583
#define RF_UART1_DATA 4*584
#define RF_UART1_LSR 4*585
#define RF_UART1_MSR 4*586
#define RF_UART1_LCR 4*587
#define RF_UART1_MCR 4*588
#define RF_UART1_DIV_L 4*589
#define RF_UART1_DIV_H 4*590
#define RF_UART1_ISC 4*591
#define RF_G18_RESERVED_16 4*592
#define RF_GPIO_MASTER_4 4*608
#define RF_GPIO_OE_4 4*612
#define RF_GPIO_OUT_4 4*616
#define RF_GPIO_IN_4 4*620
#define RF_GPIO2_INOUT_2 4*624
#define RF_GPIO2_OE_2 4*626
#define RF_G19_RESERVED1_12 4*628
#define RF_CDDSP_CONFIG 4*640
#define RF_CDDSP_CONTROL 4*641
#define RF_CDDSP_MM_BCD 4*642
#define RF_CDDSP_SS_BCD 4*643
#define RF_CDDSP_FF_BCD 4*644
#define RF_CDDSP_STATUS 4*645
#define RF_CDDSP_MMSS 4*646
#define RF_CDDSP_FFMM 4*647
#define RF_G20_RESERVED_24 4*648
#define RF_TV_GAMMA_5 4*672
#define RF_TV_PCCON_18 4*677
#define RF_G21_RESERVED_9 4*695
#define RF_MBUS_BRIDGE_CONFIG 4*704
#define RF_EVBYA 4*705
#define RF_OSDYA 4*706
#define RF_CDWYA 4*707
#define RF_CDRYA 4*708
#define RF_SUPYA 4*709
#define RF_EVBYA_LIMIT 4*710
#define RF_OSDYA_LIMIT 4*711
#define RF_CDWYA_LIMIT 4*712
#define RF_CDRYA_LIMIT 4*713
#define RF_SUPYA_LIMIT 4*714
#define RF_BS_YSTOP 4*715
#define RF_BS_RY 4*716
#define RF_BS_YINIT 4*717
#define RF_BS_XINIT 4*718
#define RF_DVDDSP_VY 4*719
#define RF_DVDDSP_VX 4*720
#define RF_DVDDSP_RY 4*721
#define RF_CDR_VY 4*722
#define RF_CDR_VX 4*723
#define RF_SUPYA2 4*724
#define RF_SUPYA2_LIMIT 4*725
#define RF_IOPYA 4*726
#define RF_CDRYA_XLIMIT 4*727
#define RF_G22_RESERVED_8 4*728
#define RF_G23_VPP_CONTRAST_ADJ_2 4*736
#define RF_G23_VPP_CONTRAST_SLOPE_3 4*738
#define RF_G23_VPP_HISTOGRAM_8 4*741
#define RF_G23_VPP_CHKSUM 4*749
#define RF_G23_VPP_MV_PTR 4*750
#define RF_G23_VPP_HUE_ADJ_2 4*751
#define RF_G23_RESERVED_15 4*753
#define RF_BUFCTL_8 4*768
#define RF_G24_RESERVED_24 4*776
#define RF_INVQ_QMX_PAR 4*800
#define RF_INVQ_MODE 4*801
#define RF_INVQ_CHKSUM 4*802
#define RF_G25_RESERVED_29 4*803
#define RF_ROM_CONFIG 4*832
#define RF_WAIT_CYC1_0 4*833
#define RF_WAIT_CYC3_2 4*834
#define RF_OE_WAIT_CYC1_0 4*835
#define RF_OE_WAIT_CYC3_2 4*836
#define RF_WE_WAIT_CYC1_0 4*837
#define RF_WE_WAIT_CYC3_2 4*838
#define RF_IOCHRDY_WAIT_CYC 4*839
#define RF_ROM1_BASE 4*840
#define RF_ROM2_BASE 4*841
#define RF_ROM3_BASE 4*842
#define RF_PCMCIA_IORW_WAIT 4*843
#define RF_PCMCIA_CTRL 4*844
#define RF_G26_RESERVED1_8 4*845
#define RF_ADT_4 4*853
#define RF_DAT_4 4*857
#define RF_ADM_2 4*861
#define RF_DAR 4*863
#define RF_SBAR_CONFIG 4*864
#define RF_SBAR_PRR_16 4*865
#define RF_G27_RESERVED_15 4*881
#define RF_RF_SDRAMIF_TBYA 4*896
#define RF_RF_SERVO_BAND_EN 4*897
#define RF_RF_SERVO_BAND_VAL 4*898
#define RF_G28_RESERVED_29 4*899
#define RF_RF_REGIF_ADDR 4*928
#define RF_RF_REGIF_WDATA 4*929
#define RF_RF_REGIF_RDATA 4*930
#define RF_RF_REGIF_SAMPLE_CTRL 4*931
#define RF_RF_REGIF_INTR_ADDR 4*932
#define RF_RF_REGIF_INTR_WDATA 4*933
#define RF_RF_REGIF_INTR_RDATA 4*934
#define RF_G29_RESERVED_25 4*935
#define RF_EMU_CFG_32 4*960
#define RF_AUD_RESET 4*992
#define RF_AUD_PCM_CFG 4*993
#define RF_AUD_SPDIF_CFG 4*994
#define RF_AUD_ENABLE 4*995
#define RF_AUD_ADC_STEREO_CFG 4*996
#define RF_AUD_ADC_MONO_CFG 4*997
#define RF_AUD_PCM_RAMP_DELTA 4*998
#define RF_AUD_PCM_RAMP_CFG 4*999
#define RF_AUD_PCM_RAMP_VALUE 4*1000
#define RF_AUD_SPDIF_PERIOD 4*1001
#define RF_AUD_FIFO_FLAG 4*1002
#define RF_AUD_CHN_PCM_CNT_10 4*1003
#define RF_AUD_XCK_CFG 4*1013
#define RF_AUD_PCM_BCK_CFG 4*1014
#define RF_AUD_IEC_BCLK_CFG 4*1015
#define RF_AUD_ADC_MCLK_CFG 4*1016
#define RF_AUD_DSP_RUN_CNT 4*1017
#define RF_AUD_DSP_STALL_CNT 4*1018
#define RF_AUD_DSP_RESET_FLAG 4*1019
#define RF_AUD_DSP_DEC_CNT_TOGGLE 4*1020
#define RF_AUD_DSP_DEC_CNT 4*1021
#define RF_AUD_FPGA_V2_2 4*1022
#define RF_G32_RESERVED_32 4*1024
#define RF_G33_RESERVED_32 4*1056
#define RF_G34_RESERVED_32 4*1088
#define RF_G35_RESERVED_32 4*1120
#define RF_G36_RESERVED_32 4*1152
#define RF_G37_RESERVED_32 4*1184
#define RF_G38_RESERVED_32 4*1216
#define RF_G39_RESERVED_32 4*1248
#define RF_SDC_REQ_T_RESET 4*1280
#define RF_SDC_REQ_TIME_14_2 4*1281
#define RF_G40_RESERVED_3 4*1309
#define RF_SDC_DATA_CNT_14_2 4*1312
#define RF_SDC_N_REQ_CNT_2 4*1340
#define RF_SDC_CKE_CNT_2 4*1342
#define RF_G42_RESERVED_32 4*1344
#define RF_G43_RESERVED_32 4*1376
#define RF_G44_RESERVED_32 4*1408
#define RF_G45_RESERVED_32 4*1440
#define RF_G46_RESERVED_32 4*1472
#define RF_G47_RESERVED_32 4*1504
#define RF_G48_RESERVED_32 4*1536
#define RF_G49_RESERVED_32 4*1568
#define RF_G50_RESERVED_29 4*1600
#define RF_RISC_FPGA_VERSION_3 4*1629
#define RF_G51_RESERVED_29 4*1632
#define RF_BLOCK_FPGA_VERSION_3 4*1661
#define RF_G52_RESERVED_29 4*1664
#define RF_AUD_FPGA_VERSION_3 4*1693
#define RF_G53_RESERVED_32 4*1696
#define RF_G54_RESERVED_32 4*1728
#define RF_G55_RESERVED_32 4*1760
#define RF_G56_RESERVED_32 4*1792
#define RF_G57_RESERVED_32 4*1824
#define RF_G58_RESERVED_32 4*1856
#define RF_G59_RESERVED_32 4*1888
#define RF_G60_RESERVED_32 4*1920
#define RF_G61_RESERVED_32 4*1952
#define RF_G62_RESERVED_32 4*1984
#define RF_G63_RESERVED_32 4*2016
#define RF_GXX_RESERVED_192_32 4*2048
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