regmapa_8200.h

Sunplus 8202S source code.

#define RF_STAMP                                 4*0
#define RF_EMULATION                             4*1
#define RF_RESET                                 4*2
#define RF_RESET2                                4*3
#define RF_PAD_CTRL                              4*4
#define RF_SDRAM_CLKO_CFG                        4*5
#define RF_SDRAM_CLKI_CFG                        4*6
#define RF_SDRAM_CLKI_DLY_CFG                    4*7
#define RF_CLK_MON_SEL                           4*8
#define RF_CLK_MON_RESULT                        4*9
#define RF_CLKEN0                                4*10
#define RF_CLKEN1                                4*11
#define RF_GCLKEN0                               4*12
#define RF_GCLKEN1                               4*13
#define RF_SYSCLK_DIV_SEL                        4*14
#define RF_SYSCLK_SEL                            4*15
#define RF_PLLV_CFG                              4*16
#define RF_SFT_CFG0                              4*17
#define RF_SFT_CFG1                              4*18
#define RF_SFT_CFG2                              4*19
#define RF_SFT_CFG3                              4*20
#define RF_SFT_CFG4                              4*21
#define RF_SFT_CFG5                              4*22
#define RF_SFT_CFG6                              4*23
#define RF_SFT_CFG7                              4*24
#define RF_SFT_CFG8                              4*25
#define RF_HW_BO                                 4*26
#define RF_HW_CFG                                4*27
#define RF_HW_CFG_CHG                            4*28
#define RF_SFT_CFG9                              4*29
#define RF_SFT_CFGA                              4*30
#define RF_G0_RESERVED_1_1                       4*31
#define RF_STC_15_0                              4*32
#define RF_STC_31_16                             4*33
#define RF_STC_32                                4*34
#define RF_STC_DIVISOR                           4*35
#define RF_RTC_15_0                              4*36
#define RF_RTC_31_16                             4*37
#define RF_RTC_DIVISOR                           4*38
#define RF_STC_CONFIG                            4*39
#define RF_TIMER0_CTRL                           4*40
#define RF_TIMER0_CNT                            4*41
#define RF_TIMER1_CTRL                           4*42
#define RF_TIMER1_CNT                            4*43
#define RF_TIMERW_CTRL                           4*44
#define RF_TIMERW_CNT                            4*45
#define RF_G1_UNUSED_1_2                         4*46
#define RF_TIMER2_CTRL                           4*48
#define RF_TIMER2_DIVISOR                        4*49
#define RF_TIMER2_RELOAD                         4*50
#define RF_TIMER2_CNT                            4*51
#define RF_TIMER3_CTRL                           4*52
#define RF_TIMER3_DIVISOR                        4*53
#define RF_TIMER3_RELOAD                         4*54
#define RF_TIMER3_CNT                            4*55
#define RF_STCL_0                                4*56
#define RF_STCL_1                                4*57
#define RF_STCL_2                                4*58
#define RF_ATC_0                                 4*59
#define RF_ATC_1                                 4*60
#define RF_ATC_2                                 4*61
#define RF_G1_RESERVED_2                         4*62
#define RF_INTR_MASK                             4*64
#define RF_INTR_FLAG                             4*65
#define RF_INTR_MASKED_FLAG                      4*66
#define RF_INTR_CLEAR                            4*67
#define RF_INTR_POLARITY                         4*68
#define RF_INTR_EDGE                             4*69
#define RF_INTR1_MASK                            4*70
#define RF_INTR1_FLAG                            4*71
#define RF_INTR1_MASKED_FLAG                     4*72
#define RF_INTR1_CLEAR                           4*73
#define RF_INTR1_POLARITY                        4*74
#define RF_INTR1_EDGE                            4*75
#define RF_LBC_CONTROL                           4*76
#define RF_LBC_WATCHDOG                          4*77
#define RF_REC_START                             4*78
#define RF_REC_END                               4*79
#define RF_REC_L_M                               4*80
#define RF_G2_RESERVED_13                        4*81
#define RF_RI_MISC_B0                            4*94
#define RF_RI_MISC_B1                            4*95
#define RF_SEQ_EXT                               4*96
#define RF_H_SIZE                                4*97
#define RF_V_SIZE                                4*98
#define RF_G3_UNUSED                             4*99
#define RF_PIC_CODING_TYPE                       4*100
#define RF_PIC_F_CODE                            4*101
#define RF_PIC_CODING_EXT0                       4*102
#define RF_PIC_CODING_EXT1                       4*103
#define RF_PIC_START                             4*104
#define RF_DIS_PIC_ID                            4*105
#define RF_DIS_SEQ_TAG                           4*106
#define RF_G3_RESERVED_21                        4*107
#define RF_VLD_CTRL                              4*128
#define RF_VLD_STATUS                            4*129
#define RF_VLD_DECODE_TIME                       4*130
#define RF_G4_UNUSED                             4*131
#define RF_VLD_MON0                              4*132
#define RF_VLD_MON1                              4*133
#define RF_VLD_MON2                              4*134
#define RF_VLD_MON3                              4*135
#define RF_JPEG_CONTROL                          4*136
#define RF_JPEG_WRITE_ADDR                       4*137
#define RF_JPEG_WRITE_DATA                       4*138
#define RF_JPEG_READ_ADDR                        4*139
#define RF_JPEG_READ_DATA                        4*140
#define RF_ERROR_MB_THRESHOLD                    4*141
#define RF_VLD_CONFIG                            4*142
#define RF_G4_RESERVED_17                        4*143
#define RF_MC_CONFIG                             4*160
#define RF_REF0_LUMA                             4*161
#define RF_REF0_CHROMA                           4*162
#define RF_REF1_LUMA                             4*163
#define RF_REF1_CHROMA                           4*164
#define RF_BIDIR_LUMA                            4*165
#define RF_BIDIR_CHROMA                          4*166
#define RF_G5_RESERVED_17                        4*167
#define RF_MC_SPARE_0                            4*184
#define RF_MC_COMPRESS                           4*185
#define RF_MC_PARDEC_START                       4*186
#define RF_MC_PARDEC_END                         4*187
#define RF_MC_MBWIDTH                            4*188
#define RF_MC_PARDEC_EN                          4*189
#define RF_MC_SPARE_6                            4*190
#define RF_MC_SPARE_7                            4*191
#define RF_SDCTRL_CFG0                           4*192
#define RF_SDCTRL_CFG1                           4*193
#define RF_SDCTRL_CFG2                           4*194
#define RF_SDCTRL_MRS                            4*195
#define RF_SDCTRL_SREF_CFG                       4*196
#define RF_SDCTRL_CFG3                           4*197
#define RF_SDCTRL_DATA_MON_ST                    4*198
#define RF_SDCTRL_DATA_CYC_L                     4*199
#define RF_SDCTRL_DATA_CYC_H                     4*200
#define RF_SDCTRL_DATA_CNT_L                     4*201
#define RF_SDCTRL_DATA_CNT_H                     4*202
#define RF_SDCTRL_GCLK_DIS                       4*203
#define RF_SDCTRL_AREF1_CFG                      4*204
#define RF_SDCTRL_INT                            4*205
#define RF_SDCTRL_INT_MASK                       4*206
#define RF_SDCTRL_INT_STATUS                     4*207
#define RF_SDCTRL_LMEM_BASE                      4*208
#define RF_SDCTRL_LMEM_ROW_ST                    4*209
#define RF_G6_UNUSED_0                           4*210
#define RF_SDCTRL_CFG4                           4*211
#define RF_G6_RESERVED_10                        4*212
#define RF_SDCTRL_MISC_B0                        4*222
#define RF_SDCTRL_MISC_B1                        4*223
#define RF_DIS_X_START                           4*224
#define RF_DIS_Y_START                           4*225
#define RF_DIS_X_SIZE                            4*226
#define RF_DIS_Y_SIZE                            4*227
#define RF_V_OFFSET                              4*228
#define RF_H_OFFSET                              4*229
#define RF_VPP_BG_Y                              4*230
#define RF_VPP_BG_CB_CR                          4*231
#define RF_V_FILTER0_SETUP                       4*232
#define RF_V_FILTER1_SETUP                       4*233
#define RF_H_FILTER_SETUP                        4*234
#define RF_VPP_CONFIG                            4*235
#define RF_VPP_CONFIG1                           4*236
#define RF_DS_FIELD_CONFIG                       4*237
#define RF_DIP_CONFIG                            4*238
#define RF_DIP_PARAM                             4*239
#define RF_DIP_MV_PTR                            4*240
#define RF_VPPREF0_LUMA                          4*241
#define RF_VPPREF0_CHROMA                        4*242
#define RF_VPPREF1_LUMA                          4*243
#define RF_VPPREF1_CHROMA                        4*244
#define RF_VPPBIDIR_LUMA                         4*245
#define RF_VPPBIDIR_CHROMA                       4*246
#define RF_DIP_REF_BASE                          4*247
#define RF_DIP_PARAM_THRESHOLD                   4*248
#define RF_DIP_PARAM_FADING                      4*249
#define RF_VPP_ACT_REGION_TOP                    4*250
#define RF_VPP_ACT_REGION_BOTTOM                 4*251
#define RF_VPP_SPARE_0                           4*252
#define RF_VPP_CLUT_AY                           4*253
#define RF_VPP_CLUT_UV                           4*254
#define RF_VPP_SPARE_1                           4*255
#define RF_TV_MODE_6                             4*256
#define RF_TV_SUBC_F_2                           4*262
#define RF_TV_SUBC_P                             4*264
#define RF_TV_LINE_T_2                           4*265
#define RF_TV_LINE_B_2                           4*267
#define RF_TV_CC_T                               4*269
#define RF_TV_CC_B                               4*270
#define RF_TV_CGMS_2                             4*271
#define RF_TV_ID_STATUS                          4*273
#define RF_TV_DAC_2                              4*274
#define RF_TV_MISC_12                            4*276
#define RF_DSP24_CONTROL                         4*288
#define RF_DSP3DBG_MODE                          4*289
#define RF_DSP3DBG_BREAK                         4*290
#define RF_DSP3DBG_ADDR                          4*291
#define RF_DSP3DBG_STEP                          4*292
#define RF_DSP3DBG_RD_L                          4*293
#define RF_DSP3DBG_RD_H                          4*294
#define RF_DSP3DBG_WR_L                          4*295
#define RF_DSP3DBG_WR_H                          4*296
#define RF_DSP3DBG_PC                            4*297
#define RF_ROM_L                                 4*298
#define RF_ROM_H                                 4*299
#define RF_DSP24YA                               4*300
#define RF_PCMYA                                 4*301
#define RF_AUDYA                                 4*302
#define RF_G9_RESERVED                           4*303
#define RF_DSP24_PORT_16                         4*304
#define RF_OSD_TV_STD                            4*320
#define RF_OSD_TV_OUT                            4*321
#define RF_OSD_MIXER                             4*322
#define RF_OSD_DISPLAY_STATUS                    4*323
#define RF_OSD_EN                                4*324
#define RF_OSD_TLINK_ADDR                        4*325
#define RF_OSD_BLINK_ADDR                        4*326
#define RF_Y_CLIP                                4*327
#define RF_CB_CLIP                               4*328
#define RF_OSD_BASE_ADDR                         4*329
#define RF_OSD_MODE_12                           4*330
#define RF_G10_RESERVED_10                       4*342
#define RF_GRAPH_MODE                            4*352
#define RF_GRAPH_STATUS                          4*353
#define RF_DMA_MODE                              4*354
#define RF_DMA_XADDR                             4*355
#define RF_DMA_YADDR                             4*356