sdctrl.inc

Sunplus 8202S source code.

// set_sdram_timing
//
                .ent    set_sdram_timing
set_sdram_timing:
#ifndef PROBE_SDRAM
                li      t3, SDCTRL_CFG4_VAL_SET
                sw      t3, RF_SDCTRL_CFG4(s6)
                jr      ra
#endif



#ifdef  SPHE8202
                // sphe8202
                lw      t1, RF_SFT_CFG8(s6)
                andi    t1, 0x0FFF
                ori     t1, 0x1000
                sw      t1, RF_SFT_CFG8(s6)             // ROM-SDRAM delay max.
                
#ifdef  IC_8202E                                        // chyeh 2005/01/05  
                lw      t2, RF_SDCTRL_MISC_B0(s6)
                ori     t2, (1<<15)                     // Use 3-stage pipeline
                sw      t2, RF_SDCTRL_MISC_B0(s6)    
#endif

#if 0
                lw      t2, RF_SDCTRL_MISC_B0(s6)
                ori     t2, (1<<1)
                sw      t2, RF_SDCTRL_MISC_B0(s6)       // Force SDRAM output always
#endif

#else

                // sphe8200
#ifdef SDRAM_BUS_32BITS
                li      t0, 0x5A;
                sw      t0, RF_PAD_CTRL(s6)             // Control pins: full-power
                                                        // DQ pins: 8mA
#endif
#endif

                // new style timing setting                
                la      t0, CFG_sdram_config            // (t0): SDRAM config table (in init0.S)
#ifdef SPHE8202                
                lw      t2, RF_STAMP(s6)
                li      t1, 0x82                        //  PS2.1 stamp:0x82 ,terry,2005/1/30 08:14PM
                bne     t2,t1,9f
                la      t0, CFG_sdram_config_PS21       // (t0): SDRAM config table (in init0.S)                
9:             
#endif
 
#if defined(SPHE8202)||defined(SPHE1000)
                lhu     t1, 0(t0)                       // get OUT cfg
                lhu     t2, 2(t0)                       // get IN cfg
                lhu     t3, 4(t0)                       // get IN_DLY cfg
                lhu     t4, 6(t0)                       // get PADCTRL cfg
                sw      t1, RF_SDRAM_CLKO_CFG(s6)       // write OUT cfg
                sw      t2, RF_SDRAM_CLKI_CFG(s6)       // write IN cfg
                sw      t3, RF_SDRAM_CLKI_DLY_CFG(s6)   // write IN_DLY cfg
                sw      t4, RF_PAD_CTRL(s6)             // write PADCTRL cfg
                
#else
                lhu     t1, 0(t0)                       // get OUT cfg
                lhu     t2, 2(t0)                       // get IN cfg
                sw      t1, RF_SDRAM_CLKO_CFG(s6)       // write OUT cfg
                sw      t2, RF_SDRAM_CLKI_CFG(s6)       // write IN cfg
#endif

#ifdef SDRAM_DBG //terry,2005/1/31 09:52AM
                lw      a0, RF_STAMP(s6);PUTA0
                move    a0,t0;PUTA0
                move    a0,t1;PUTA0
                move    a0,t2;PUTA0
                move    a0,t3;PUTA0
                move    a0,t4;PUTA0
#endif


#if 0
#define     MON_SDRAM_CLK_O 5
#define     MON_SDRAM_CASB  6
//                li      t0, ((5<<2)|2)
//                li      t0, ((1<<2)|2)          // sdram_clk_o
//                li      t0, ((6<<2)|1)              // casb falling
                li      t0, ((2<<2)|2)          // sdram_clk_i
                sw      t0, RF_CLK_MON_SEL(s6)
                li      t0, 4096    
1:              addiu   t0, -1                            // wait 1024 cycles for mrs
                bnez    t0, 1b
                lw      a0, RF_CLK_MON_RESULT(s6)
                PUTA0
#endif

                jr      ra
                .end    set_sdram_timing


//
// FUNCTION
// set_sdram_timing_low()
//
// DESCRIPTION
// System low-speed SDRAM timing setting
//
                .ent    set_sdram_timing_low
set_sdram_timing_low:
                li v0,(0x04<<3)|(0x00); sw v0,RF_SDRAM_CLKO_CFG(s6)
                li v0,(0x04<<3)|(0x00); sw v0,RF_SDRAM_CLKI_CFG(s6)
                li v0,(0x00); sw v0,RF_SDRAM_CLKI_DLY_CFG(s6)
                jr      ra
                .end    set_sdram_timing_low


//
// FUNCTION
// probe_sdram_type
//
// DESCRIPTION
// This function will probe SDRAM type from 256MB to 16MB
// and set RF_SDCTRL_CFG3 register accordingly.
//
// *NOTE*
// 1. Default value SDCTRL_CFG3_VAL_DEF will be used.
// 2. Assume x16 and 2-SDRAM configuration.
//
#define    SDRAM_BASE_TESTED    0xA0000000

                .ent    probe_sdram_type
flush_lbc_buffer:
                WRITESTAMP(STAMP_SDRAM_PROBE | 0x80)
                li      v0, 3
                sw      v0, RF_LBC_CONTROL(s6)
1:
                lw      v0, RF_LBC_CONTROL(s6)
                andi    v0, 1
                bnez    v0, 1b
                jr      ra

error_sdram:
#ifdef BOOTSTRAP_WRITE_UART
                PUTC('E'); PUTC('R'); PUTC('R');
                PUTCR(v0);
                PUTC(0x0d); PUTC(0x0a)

                li      v0, 0x00000000
                sw      v0, (t3)
                jal     flush_lbc_buffer
                lw      a0, (t3)
                PUTA0

                li      v0, 0xffffffff
                sw      v0, (t3)
                jal     flush_lbc_buffer
                lw      a0, (t3)
                PUTA0

                li      v0, 0x01234567
                sw      v0, (t3)
                jal     flush_lbc_buffer
                lw      a0, (t3)
                PUTA0

                li      v0, 0xabcdef01
                sw      v0, (t3)
                jal     flush_lbc_buffer
                lw      a0, (t3)
                PUTA0

1:
                li      v0, 0x01234567
                sw      v0, (t3)
                jal     flush_lbc_buffer
                b       1b
#endif
#ifdef ERROR_SDRAM_PROBE
                .extern test_sdram
                j       test_sdram
#endif
                WRITESTAMP(STAMP_SDRAM_PROBE_ERROR)
1:
                b       1b

probe_sdram_type:
                move    a3, ra
                li      t1, 0x01234567            // t1: tag #1
                li      t2, 0xfedcba98            // t2: tag #2
                la      t3, 0xA0000000            // t3: sdram startingpoint

                // default to 4-bank and max row/column
                li      t7, SDCTRL_CFG4_CW(13)|SDCTRL_CFG4_RW(13)|SDCTRL_CFG4_PALL(10)|SDCTRL_CFG4_BANK4(1)
                sw      t7, RF_SDCTRL_CFG4(s6)
                sw      zero, (t3)              // store 0 to column 0

                li      t4, 6                   // scan from 6: (col=a0~a6)
#ifdef SDRAM_BUS_32BITS
                li      t6, 128*2*4             // 128 2-bank 32-bit 
#else
                li      t6, 128*2*2             // 128 2-bank 16-bit
#endif
1:
                addu    t7, t3, t6
                sw      t1, (t7)                // store tag#1 column +256/512/....
                jal     flush_lbc_buffer
                lw      t7, (t3)                // reload column 0
#ifdef  BOOTSTRAP_WRITE_UART
                move a0, t7; PUTA0
#endif
                bnez    t7, column_probed       // has been overwrittened by something

                addiu   t4, 1
                sll     t6, 1
                b       1b

column_probed:
                li      v0, '0'
                bne     t7, t1, error_sdram

                WRITESTAMP(STAMP_SDRAM_PROBE | 2)

                /*
                ** PROBE ROW
                */
                // set to cw=a0~a5 (64w)
                li      t7, SDCTRL_CFG4_CW(5)|SDCTRL_CFG4_RW(15)|SDCTRL_CFG4_PALL(10)|SDCTRL_CFG4_BANK4(1)
                sw      t7, RF_SDCTRL_CFG4(s6)
                sw      zero, (t3)              // store 0 to column 0 (t3)

                li      t5, 6<<4                // row: a0~a6
#ifdef SDRAM_BUS_32BITS
                li      t6, 128*64*2*4          // bank 2 column 64 width 4
#else
                li      t6, 128*64*2*2          // bank 2 column 64 width 2
#endif
2:
                addu    t7, t3, t6
                sw      t1, (t7)                // store row+t6
                jal     flush_lbc_buffer
                lw      t7, (t3)                // load row0
#ifdef  BOOTSTRAP_WRITE_UART
                move a0, t7; PUTA0
#endif
                bnez    t7, row_probed

                addiu   t5, 1<<4
                sll     t6, 1
                b       2b

row_probed:
                li      v0, '1'
                bne     t7, t1, error_sdram
                or      t4, t5                    // save to t4

                WRITESTAMP(STAMP_SDRAM_PROBE | 3)
                
                /*
                ** PROBE BANK
                */
                // set to cw=a0~a5 (64w)  rw=a0~a1
                li      t7, SDCTRL_CFG4_CW(5)|SDCTRL_CFG4_RW(1)|SDCTRL_CFG4_PALL(10)|SDCTRL_CFG4_BANK4(1)
                sw      t7, RF_SDCTRL_CFG4(s6)
                sw      zero, (t3)                // store column 0

#ifdef SDRAM_BUS_32BITS
                li      t6, 64*4*2*4
#else
                li      t6, 64*4*2*2
#endif

                addu    t7, t3, t6
                sw      t1, (t7)                // load column +256/512/....
                jal     flush_lbc_buffer
                lw      t7, (t3)                // load column 0
                bnez    t7, bank_probed
                ori     t4, SDCTRL_CFG4_BANK4(1)
bank_probed:

                WRITESTAMP(STAMP_SDRAM_PROBE | 4)

                /*
                ** PROBE FINISHED
                */
                ori     t4, SDCTRL_CFG4_PALL(10)
                sw      t4, RF_SDCTRL_CFG4(s6)

                jr      a3
                .end    probe_sdram_type