timer_macro.h

the timer control demo source for the NEC mcu

/*
*******************************************************************************
**
**  This device driver was created by Applilet for the 78K0/KB2, 78K0/KC2,
**  78K0/KD2, 78K0/KE2 and 78K0/KF2 8-Bit Single-Chip Microcontrollers.
**
**  Filename :	timer.h
**  Abstract :	This file implements a device driver for the timer module
**  Device :	uPD78F0547
**  Compiler:	NEC/CC78K0
**
*******************************************************************************
*/

#ifndef _TIMERMACRO_
#define _TIMERMACRO_

/*
*******************************************************************************
**  Register bit define
*******************************************************************************
*/

/* TM0n register bit define */

/* TM0n register TMC0n */
#define	TM0n_TMC0n_Operation	0x0c
	#define	TM0n_TMC0n_Operation_Disable	0x00
	#define	TM0n_TMC0n_Operation_FreeRunning	0x04
	#define	TM0n_TMC0n_Operation_ClearByTI00nEdge	0x08
	#define	TM0n_TMC0n_Operation_ClearByMatchCR00n	0x0c

#define	TM0n_TMC0n_Reverse	0x02
	#define	TM0n_TMC0n_Reverse_ByMatchCR00n	0x00
	#define	TM0n_TMC0n_Reverse_ByMatchCR00nAndTI00nInput	0x02

#define	TM0n_TMC0n_OverflowFlag	0x01

/* TM0n register CRC0n */
#define	TM0n_CRC0n_CR01nMode	0x04
	#define	TM0n_CRC0n_CR01nMode_Compare	0x00
	#define	TM0n_CRC0n_CR01nMode_Capture	0x04

#define	TM0n_CRC0n_CR00nTrigger	0x02
	#define	TM0n_CRC0n_CR00nTrigger_TI01nEdge	0x00
	#define	TM0n_CRC0n_CR00nTrigger_TI00nEdgeReverse	0x02

#define	TM0n_CRC0n_CR00nMode	0x01
	#define	TM0n_CRC0n_CR00nMode_Compare	0x00
	#define	TM0n_CRC0n_CR00nMode_Capture	0x01

/* TM0n register TOC0n */
#define	TM0n_TOC0n_OneshotSoftTrigger	0x40	/* write only */

#define	TM0n_TOC0n_OneshotMode	0x20
	#define	TM0n_TOC0n_OneshotMode_Successive	0x00
	#define	TM0n_TOC0n_OneshotMode_Oneshot	0x20

#define	TM0n_TOC0n_ReverseTO0nByCR01n	0x10
	#define	TM0n_TOC0n_ReverseTO0nByCR01n_Disable	0x00
	#define	TM0n_TOC0n_ReverseTO0nByCR01n_Enable	0x10

#define	TM0n_TOC0n_TO0nOutStatus	0x0C
	#define	TM0n_TOC0n_TO0nOut_NoChange	0x00
	#define	TM0n_TOC0n_TO0nOut_Clear0	0x04
	#define	TM0n_TOC0n_TO0nOut_Set1	0x08
	#define	TM0n_TOC0n_TO0nOut_Prohibited	0x0C

#define	TM0n_TOC0n_TO0nReverseByCR00n	0x02
	#define	TM0n_TOC0n_TO0nReverseByCR00n_Disable	0x00
	#define	TM0n_TOC0n_TO0nReverseByCR00n_Enable	0x02

#define	TM0n_TOC0n_TO0nOutControl	0x01
	#define	TM0n_TOC0n_TO0nOut_Disable	0x00
	#define	TM0n_TOC0n_TO0nOut_Enable	0x01

/* TM0n register PRM0n */
#define	TM0n_PRM0n_TI01nEdge	0xc0
	#define	TM0n_PRM0n_TI01nEdge_Falling	0x00
	#define	TM0n_PRM0n_TI01nEdge_Rising	0x40
	#define	TM0n_PRM0n_TI01nEdge_Prohibited	0x80
	#define	TM0n_PRM0n_TI01nEdge_Both	0xc0

#define	TM0n_PRM0n_TI00nEdge	0x30
	#define	TM0n_PRM0n_TI00nEdge_Falling	0x00
	#define	TM0n_PRM0n_TI00nEdge_Rising	0x10
	#define	TM0n_PRM0n_TI00nEdge_Prohibited	0x20
	#define	TM0n_PRM0n_TI00nEdge_Both	0x30

#define	TM0n_PRM0n_CountClock	0x03
	#define	TM0n_PRM0n_CountClock_Internal0	0x00	/* TM00 = fprs, TM00 = fprs */
	#define	TM0n_PRM0n_CountClock_Internal1	0x01	/* TM00 = fprs/2^2, TM00 = fprs/2^4 */
	#define	TM0n_PRM0n_CountClock_Internal2	0x02	/* TM00 = fprs/2^8, TM00 = fprs/2^6 */
	#define	TM0n_PRM0n_CountClock_TI00nEdge	0x03

/* TM5n register bit define */

/* TM5n register TCL5n */
#define	TM5n_TCL5n_CountCloc	0x07
	#define	TM5n_TCL5n_CountClock_TI5nFalling	0x00
	#define	TM5n_TCL5n_CountClock_TI5nRising	0x01
	#define	TM5n_TCL5n_CountClock_Internal0	0x02	/* TM50 = fprs, TM51 = fprs */
	#define	TM5n_TCL5n_CountClock_Internal1	0x03	/* TM50 = fprs/2, TM51 = fprs/2 */
	#define	TM5n_TCL5n_CountClock_Internal2	0x04	/* TM50 = fprs/2^2, TM51 = fprs/2^4 */
	#define	TM5n_TCL5n_CountClock_Internal3	0x05	/* TM50 = fprs/2^6, TM51 = fprs/2^6 */
	#define	TM5n_TCL5n_CountClock_Internal4	0x06	/* TM50 = fprs/2^8, TM51 = fprs/2^8 */
	#define	TM5n_TCL5n_CountClock_Internal5	0x07	/* TM50 = fprs/2^13, TM51 = fprs/2^12 */

/* TM5n register TMC5n */
#define	TM5n_TMC5n_Operation	0x80
	#define	TM5n_TMC5n_Operation_Disable	0x00
	#define	TM5n_TMC5n_Operation_Start	0x80

#define	TM5n_TMC5n_Mode	0x40
	#define	TM5n_TMC5n_Mode_ClearByMatchCR5n	0x00
	#define	TM5n_TMC5n_Mode_PWMFreeRunning	0x40

#define	TM5n_TMC5n_OutPutStatus	0x0C
	#define	TM5n_TMC5n_OutPut_NoChange	0x00
	#define	TM5n_TMC5n_OutPut_Clear0	0x04
	#define	TM5n_TMC5n_OutPut_Set1	0x08
	#define	TM5n_TMC5n_OutPut_Prohibited	0x0C

#define	TM5n_TMC5n_OutPutActiveLevel	0x02
	#define	TM5n_TMC5n_OutPut_NoInversionActiveHigh	0x00
	#define	TM5n_TMC5n_OutPut_InversionActiveLow	0x02

#define	TM5n_TMC5n_OutPutControl	0x01
	#define	TM5n_TMC5n_OutPut_Disable	0x00
	#define	TM5n_TMC5n_OutPut_Enable	0x01

/* TMHn register bit define */

/* TMHn register TMHMDn */
#define	TMHn_TMHMDn_Operation	0x80
	#define	TMHn_TMHMDn_Operation_Stop	0x00
	#define	TMHn_TMHMDn_Operation_Enable	0x80

#define	TMHn_TMHMDn_CountClock	0x70
	#define	TMHn_TMHMDn_CountClock_Internal0	0x00	/* TMH0 = fprs, TMH1 = fprs */
	#define	TMHn_TMHMDn_CountClock_Internal1	0x10	/* TMH0 = fprs/2, TMH1 = fprs/2 */
	#define	TMHn_TMHMDn_CountClock_Internal2	0x20	/* TMH0 = fprs/2^2, TMH1 = fprs/2^4 */
	#define	TMHn_TMHMDn_CountClock_Internal3	0x30	/* TMH0 = fprs/2^6, TMH1 = fprs/2^6 */
	#define	TMHn_TMHMDn_CountClock_Internal4	0x40	/* TMH0 = fprs/2^8, TMH1 = fprs/2^8 */
	#define	TMHn_TMHMDn_CountClock_Internal5	0x50	/* TMH0 = fprs/2^13, TMH1 = frl/2^7 */
	#define	TMHn_TMHMDn_CountClock_Internal6	0x60	/* TMH0 = fprs/2^13, TMH1 = frl/2^9 */
	#define	TMHn_TMHMDn_CountClock_Internal7	0x70	/* TMH0 = fprs/2^13, TMH1 = frl */

#define	TMHn_TMHMDn_Mode	0x0c
	#define	TMHn_TMHMDn_Mode_Interval	0x00
	#define	TMHn_TMHMDn_Mode_Carrier	0x04
	#define	TMHn_TMHMDn_Mode_PWM	0x08

#define	TMHn_TMHMDn_Level_Low	0x00
#define	TMHn_TMHMDn_Level_High	0x02

#define	TMHn_TMHMDn_OutPut_Disable	0x00
#define	TMHn_TMHMDn_Output_Enable	0x01

/* TMHn register TMCYC1(TMH1 only) */
#define	TMHn_TMCYC1_Remote	0x06
	#define	TMHn_TMCYC1_Remote_Low	0x00
	#define	TMHn_TMCYC1_Remote_High	0x02
	#define	TMHn_TMCYC1_Remote_Low2	0x04
	#define	TMHn_TMCYC1_Remote_Carrier	0x06

#define	TMHn_TMCYC1_CarrierStatus	0x01
	#define	TMHn_TMCYC1_Carrier_Disable	0x00
	#define	TMHn_TMCYC1_Carrier_Enable	0x01

#endif		/* _TIMERMACRO_*/