bfm_cc.v.bak

FPGA的一个学习用的代码。主要表示了验证环境的搭建

module bfm_cc
(
 sys_clk,
 cpu_cs_cc_n,
 cpu_oe_cc_n,
 cpu_we_cc_n,
 cpu_adr_cc,
 cpu_dat_cc,
 cc_dat_cpu 

);

input         sys_clk;

//interface between cpu and cc
output         cpu_cs_cc_n;
output         cpu_oe_cc_n;
output         cpu_we_cc_n;
output [9:0]   cpu_adr_cc;
output [31:0]  cpu_dat_cc;
input  [31:0]  cc_dat_cpu;

//interface between sigproc and cc
output [31:0]  sigproc_dat_cc;       
output         sigproc_vld_cc;    
input          cc_ack_sigproc;   
input  [31:0]  cc_dat_sigproc;
input          cc_vld_sigproc;  

//interface between datproc and cc
output         datproc_vld_cc;
output  [31:0] datproc_dat_cc;
output  [3:0]  datproc_chnl_cc;
input	[13:0] cc_empt_datproc;
input          cc_vld_datproc;
input          cc_dat_datproc;
input          cc_chnl_datproc;

//internal register defination
reg            cpu_cs_cc_n;
reg            cpu_oe_cc_n;
reg            cpu_we_cc_n;
reg    [9:0]   cpu_adr_cc;
reg    [31:0]  cpu_dat_cc;

reg     [31:0] sigproc_dat_cc;       
reg            sigproc_vld_cc;    
       
reg            datproc_vld_cc;
reg     [31:0] datproc_dat_cc;
reg     [3:0]  datproc_chnl_cc;       

initial
begin 
   cpu_cs_cc_n = 1;
   cpu_oe_cc_n = 1;
   cpu_we_cc_n = 1;
   cpu_adr_cc  = 0;
   cpu_dat_cc  = 0;

   sigproc_dat_cc = 0;       
   sigproc_vld_cc = 0;    
   
   datproc_vld_cc  = 0;
   datproc_dat_cc  = 0;
   datproc_chnl_cc = 0;
         
end

task cpu_rd_reg;
input [9:0]  addr;
begin
    @(posedge sys_clk) #2;
	cpu_cs_cc_n = 0;
	cpu_oe_cc_n = 0;
	cpu_adr_cc  = addr;
    @(posedge sys_clk) #2;
    @(posedge sys_clk) #2;
    @(posedge sys_clk) #2;
    cpu_cs_cc_n = 1;
	cpu_oe_cc_n = 1;

end
endtask


task cpu_wt_reg;
input [9:0]  addr;
input [31:0] dat;
begin
	@(posedge sys_clk) #2;
	cpu_cs_cc_n = 0;
	cpu_we_cc_n = 0;
	cpu_adr_cc  = addr;
    cpu_dat_cc  = dat;
    
    @(posedge sys_clk) #2;
    @(posedge sys_clk) #2;
    @(posedge sys_clk) #2;
    cpu_cs_cc_n = 1;
	cpu_we_cc_n = 1;

end
endtask

task sigproc_wt_dat;
input [31:0] dat;
begin
	@(posedge sys_clk) #2;
	sigproc_vld_cc = 1;
	sigproc_dat_cc = dat;
	
	wait(cc_ack_sigproc);
	@(posedge sys_clk) #2;
	sigproc_vld_cc = 0;

end
endtask

task datproc_wt_dat;
input [3:0]  chnl_num;
input [31:0] dat;
begin
    case(chnl_num)
      0:
        wait(cc_empt_datproc[0]); 
      1:
        wait(cc_empt_datproc[1]); 
      2:
        wait(cc_empt_datproc[2]); 
      3:
        wait(cc_empt_datproc[3]); 
      4:
        wait(cc_empt_datproc[4]); 
      5:
        wait(cc_empt_datproc[5]); 
      6:
        wait(cc_empt_datproc[6]); 
      7:
        wait(cc_empt_datproc[7]); 
      8:
        wait(cc_empt_datproc[8]); 
      9:
        wait(cc_empt_datproc[9]); 
      10:
        wait(cc_empt_datproc[10]); 
      11:
        wait(cc_empt_datproc[11]); 
      12:
        wait(cc_empt_datproc[12]); 
      13:
        wait(cc_empt_datproc[13]); 
      default:
        wait(cc_empt_datproc[0]); 
    endcase
	
	@(posedge sys_clk) #2;
	datproc_vld_cc  = 1;
	datproc_dat_cc  = dat;
	datproc_chnl_cc = chnl_num;

end
endtask

endmodule