📄 hdb3.v
字号:
//***********************************************
//author : Zhang Yonggang
//data: 2007.5
//preject: HDB3
//Email: zhangyonggang5@sohu.com
//************************************************
module top(rst,sin,clk,hdb3);
input rst;
input sin;
input clk;
output [2:0] hdb3;
reg [2:0] hdb3;
reg [3:0] in_buf;
reg ou;
reg fu;
reg [2:0] vshow;
reg vpose;
reg data;
parameter
Vp = 3'b111,
Bp = 3'b110,
Hp = 3'b101,
Zero = 3'b100,
Hn = 3'b011,
Bn = 3'b010,
Vn = 3'b001;
//////////////////////////////////////
always @(negedge rst or posedge clk)
if(~rst)
in_buf <=4'h0;
else
in_buf <={in_buf[2:0],sin};
//////////////////////////////////////
always @(negedge rst or negedge clk)
if(~rst)
begin
ou <=0;
fu <=0;
vshow <=3'b000;
vpose <=0;
data <=0;
end
else
begin
data<=in_buf[3];
if(in_buf[3]==0) //0xxx
if( vshow==3'b010) //x000 0xxx it's time to make v
begin
vshow <= vshow +1;
if(vpose)
begin
hdb3 <=Vn;
fu <=1;
end
else
begin
hdb3 <=Vp;
fu <=0;
end
end
else // make b time
if( in_buf==4'h0 )
if( vshow==3'b111)
begin
vshow <=3'b000;
vpose <=~vpose;
fu <=~vpose;
ou <=1;
if(ou)
if(fu)
hdb3 <=Bp;
else
hdb3 <=Bn;
else
hdb3 <=Zero;
end
else
begin
hdb3 <=Zero;
if(vshow <3'b110)
vshow <= vshow +1;
else
vshow <=3'b110;
end
else
begin
hdb3 <=Zero;
if(~vshow[2])
vshow <= vshow +1;
else
vshow <=3'b110;
end
else //1xxx
begin
vshow <=3'b111;
fu <=~fu;
ou <=~ou;
if(fu)
hdb3 <=Hp;
else
hdb3 <=Hn;
end
end
endmodule
//********************************************
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -