lowlevel_init.s

来自「华为 HI3510 BOOTLOADER HIBOOT 源码包」· S 代码 · 共 204 行

#include <config.h>
#include "platform.h"

#define DELAY_CYCLES	100

.macro	__initdata_end, name
	.word ~0x00
__INITDATA_LOCATION__\name:
	.word __INITDATA_BEGIN__\name - TEXT_BASE
.endm

#define INITDATA_BEGIN(name, base) __INITDATA_BEGIN__##name: .word (base)
#define INITDATA_END(name) __initdata_end name

.macro load_initdata, name
	mov sp, lr
	ldr r0, __INITDATA_LOCATION__\name
	bl  __load_initdata
	mov lr, sp
.endm

.macro initdata2, tag, val
	.word (\tag)
	.word (\val)
.endm

.macro initdata3, tag, val, ctl
	initdata2 (\tag), (\val)
	.word (\ctl)
.endm

#define DELAY(x) ((x)<<8)

/* lowlevel init flags */
#define LIF_ABSA  (1)
#define LIF_READ	 (1<<1)

#define LIF_ORR	 (1<<2)
#define LIF_AND	 (1<<3)
#define LIF_PRD   (1<<4)

#define OFS_REGA(x,val,ctl) initdata2 (((x)<<16) | (ctl)),	(val)

#define ABS_REGA_RO(x,ctl) initdata2 (((x)&(~0x03)) | LIF_ABSA | LIF_READ),	(ctl)
#define ABS_REGA_WR(x,val,ctl) initdata3 (((x)&(~0x03)) | LIF_ABSA), (val), (ctl)


.globl lowlevel_init
lowlevel_init:
	load_initdata SMI
	load_initdata SYSCTL
	load_initdata DDRC

	mov	pc, lr


#define initdata_ptr  r0
#define reggroup      r1
#define regaddr       r2
#define regdata       r3
#define tmp0          r4
#define tmp1          r5
#define tmp2          r6
#define tmp3          r7
#define control       r8

__load_initdata:
	/* r0: initdata base addr */
	ldr	reggroup,	[initdata_ptr, #0]

	__load_loop:
	/* load register address */
	ldr	regaddr,	[initdata_ptr, #4]!
	mvn	tmp0,		regaddr

	mov	control,	regaddr,	lsl#16
	mov	control,	control,	lsr#16

	/* check if the end */
	cmp	tmp0,		#0
	moveq	pc,		lr
	
	/* load register data */
	ldr	regdata,	[initdata_ptr, #4]!

	/* check if is abs addr */
	tst	control,	#LIF_ABSA
	beq	_offset_addr

	and	regaddr,	#(~0x03)
	tst	control,	#LIF_READ
	beq	_abs_do_write
	/* abs addr readonly */
	mov	control,	regdata
	b	_read_only
	_abs_do_write:
	ldr	control,	[initdata_ptr, #4]!
	b	_test_pre_read

	/* offset addr, make abs addr */
	_offset_addr:
	add	regaddr,	reggroup,	regaddr, lsr#16
	and	regaddr,	#(~0x03)
	tst	control,	#LIF_READ
	bne	_read_only

	_test_pre_read:
	tst	control,	#LIF_PRD 
	beq	_test_do_orr
	ldr	tmp0,		[regaddr, #0]

	_test_do_orr:
	tst	control,	#LIF_ORR
	beq	_test_do_and
	ldr	tmp1,		[regaddr, #0]
	orr	regdata,	tmp1
	b	_ready_to_write

	_test_do_and:
	tst	control,	#LIF_AND
	beq	_ready_to_write
	ldr	tmp1,		[regaddr, #0]
	and	regdata,	tmp1

	/* write regdata */
	_ready_to_write:
	str	regdata,	[regaddr, #0]
	b	_do_delay

	/* read register */
	_read_only:
	ldr	tmp0,	[regaddr, #0]

	_do_delay:
	mov	tmp0,		control,	lsr#8
	_delay_loop:
	cmp	tmp0,		#0
	beq	__load_loop

		ldr	tmp1,	=DELAY_CYCLES
		nop
	_delay_100us:
		subs	tmp1,	tmp1,	#1
		bne	_delay_100us
	subs	tmp0,	tmp0,	#1
	b	_delay_loop


INITDATA_BEGIN(SYSCTL, SYSTEM_CONTROL_BASE)
	OFS_REGA(0x003C,	0x00000004,	0)
	OFS_REGA(0x0014,	0x0fffbb40,	0)
	OFS_REGA(0x0018,	0x000023DC,	0)
	OFS_REGA(0x001C,	0x000023A0,	DELAY(10))
	OFS_REGA(0x0000,	0x00000217,	DELAY(4))
INITDATA_END(SYSCTL)

INITDATA_BEGIN(DDRC, DDRC_BASE)
	OFS_REGA(0x0038,	0x00000008,	0)
	OFS_REGA(0x0050,	0x00000000,	0)
	OFS_REGA(0x0000,	0x00000001,	0)
	OFS_REGA(0x0028,	0x00000011,	0)
	OFS_REGA(0x0104,	0x00000203,	0)

	OFS_REGA(0x0030,	0x00000002,	0)
	OFS_REGA(0x0034,	0x00000004,	0)
	OFS_REGA(0x0038,	0x000000C8,	0)
	OFS_REGA(0x0044,	0x00000001,	0)
	OFS_REGA(0x0048,	0x00000008,	0)
	OFS_REGA(0x004C,	0x00000009,	0)
	OFS_REGA(0x0050,	0x000000C8,	0)
	OFS_REGA(0x0054,	0x00000001,	0)
	OFS_REGA(0x0058,	0x00000002,	0)
	OFS_REGA(0x005C,	0x00000001,	0)

	OFS_REGA(0x0100,	0x00004684,	0)

	OFS_REGA(0x0008,	0x00000000,	0)
	OFS_REGA(0x0020,	0x00000183,	DELAY(2))
	OFS_REGA(0x0020,	0x00000103,	DELAY(2))
	OFS_REGA(0x0020,	0x00000083,	DELAY(2))
	ABS_REGA_RO(0xF0001000,	0)
	OFS_REGA(0x0020,	0x00000083,	0)
	ABS_REGA_RO(0xf0484000,	DELAY(4))
	OFS_REGA(0x0020,	0x00000103,	0)
	OFS_REGA(0x0024,	0x00000010,	DELAY(10))
	OFS_REGA(0x0020,	0x00000083,	0)

	ABS_REGA_RO(0xf0084000,	0)

	OFS_REGA(0x0020,	0x00000003,	0)
	OFS_REGA(0x0060,	0x00004002,	0)
	OFS_REGA(0x0400,	0x00000000,	0)
	OFS_REGA(0x0420,	0x00000002,	0)
	OFS_REGA(0x0440,	0x00000002,	0)
	OFS_REGA(0x0460,	0x00000000,	0)
	OFS_REGA(0x0480,	0x00000000,	0)
INITDATA_END(DDRC)

INITDATA_BEGIN(SMI, DDRC_BASE)

INITDATA_END(SMI)