📄 lowlevel_init.s
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/* Time delay 6. */ LDR r1, =0x4000flagDelay6: SUBS r1, r1, #1 BNE flagDelay6 /* Set SDRAM Initialisation Value (I) to NORMAL (MEMCDynamicControl [8:7] to 2'b00) *//* ----------------------------------------------------------------------------- */ LDR r1, =0xC003 STR r1, [r2, #MEMC_DYNAMIC_CONTROL - MEMC_BASE] /* Time delay 7. */ MOV r1, #0x100flagDelay7: SUBS r1, r1, #1 BNE flagDelay7 LDR r2, =0x10110400 LDR r1, =0x32 STR r1, [r2, #0x8] LDR r1, =0x32 STR r1, [r2, #0x28] LDR r1, =0x32 STR r1, [r2, #0x48] LDR r1, =0x32 STR r1, [r2, #0x68] LDR r1, =0x32 STR r1, [r2, #0x88] /* ----------------------------------------------------------------------------- *//* ----------------------------------------------------------------------------- *//* ----------------------------------------------------------------------------- */ /* Initialize MEMC1 for 16bits DDR SDRAM is in bank4(First dynamic bank.) *//* ----------------------------------------------------------------------------- *//* ----------------------------------------------------------------------------- *//* ----------------------------------------------------------------------------- */ LDR r2, =DDRC_BASE/* Set control register */ LDR r1, =0x1 STR r1, [r2, #DDRC_CONTROL - DDRC_BASE]/* Time delay 08. */ MOV r1, #0x100flagDelay08: SUBS r1, r1, #1 BNE flagDelay08/* dynamic read config */ LDR r1, =0x1711 STR r1, [r2, #DDRC_DYNAMIC_READCONFIG - DDRC_BASE]/* Set ddr SDRAM Initialisation Value to NOP */ LDR r1, =0xC183 STR r1, [r2, #DDRC_DYNAMIC_CONTROL - DDRC_BASE] /* Time delay 8. */ MOV r1, #0x100flagDelay8: SUBS r1, r1, #1 BNE flagDelay8 /* Set ddr SDRAM Initialisation Value to PALL */ LDR r1, =0xC103 STR r1, [r2, #DDRC_DYNAMIC_CONTROL - DDRC_BASE] /* set refresh register for a small value(32 cycles) */ LDR r1, =0x2 STR r1, [r2, #DDRC_DYNAMIC_REFRESH - DDRC_BASE]/* Time delay 9. */ MOV r1, #0x100flagDelay9: SUBS r1, r1, #1 BNE flagDelay9/* set refresh register for a big value(160 cycles) */ LDR r1, =0x22 STR r1, [r2, #DDRC_DYNAMIC_REFRESH - DDRC_BASE]/* Time delay 91. */ MOV r1, #0x100flagDelay91: SUBS r1, r1, #1 BNE flagDelay91/* Program RAS/CAS latency */ LDR r1, =0x202 STR r1, [r2, #DDRC_DYNAMIC_RASCAS(0) - DDRC_BASE] /* Write operational value into Config register */ LDR r1, =DDRC_CONFIG_VALUE STR r1, [r2, #DDRC_DYNAMIC_CONFIG(0) - DDRC_BASE]/* Set SDRAM Initialisation Value to MODE */ LDR r1, =0xC083 STR r1, [r2, #DDRC_DYNAMIC_CONTROL - DDRC_BASE]/* Program the Extend Mode Register */ //LDR r5, =0xf0001000 LDR r5, =DDR_EXTEND_MODE LDR r0, [r5]/* Program the Mode registers */ LDR r5, =DDR_MODE_REGISTER1 LDR r0, [r5] /* Time delay 10. */ MOV r1, #0x100flagDelay10: SUBS r1, r1, #1 BNE flagDelay10/* Setup Dynamic registers */ LDR r1, =0x1 STR r1, [r2, #DDRC_DYNAMIC_TRP - DDRC_BASE] //LDR r1, =0x2 LDR r1, =0x4 STR r1, [r2, #DDRC_DYNAMIC_TRAS - DDRC_BASE] //LDR r1, =0x5 LDR r1, =0x7f STR r1, [r2, #DDRC_DYNAMIC_TSREX - DDRC_BASE] //LDR r1, =0x2 LDR r1, =0x01 STR r1, [r2, #DDRC_DYNAMIC_TWR - DDRC_BASE] //LDR r1, =0x4 LDR r1, =0x06 STR r1, [r2, #DDRC_DYNAMIC_TRC - DDRC_BASE] //LDR r1, =0x4 LDR r1, =0x07 STR r1, [r2, #DDRC_DYNAMIC_TRFC - DDRC_BASE] //LDR r1, =0xc8 LDR r1, =0xff STR r1, [r2, #DDRC_DYNAMIC_TXSR - DDRC_BASE] //LDR r1, =0x1 LDR r1, =0x01 STR r1, [r2, #DDRC_DYNAMIC_TRRD - DDRC_BASE] //LDR r1, =0x2 LDR r1, =0x02 STR r1, [r2, #DDRC_DYNAMIC_TMRD - DDRC_BASE] LDR r1, =0x1 STR r1, [r2, #DDRC_DYNAMIC_TCDLR - DDRC_BASE]/* Time delay 12. */ MOV r1, #0x100flagDelay12: SUBS r1, r1, #1 BNE flagDelay12/* Set SDRAM Initialisation Value to PALL */ LDR r1, =0xC103 STR r1, [r2, #DDRC_DYNAMIC_CONTROL - DDRC_BASE]/* Time delay 13. */ MOV r1, #0x100flagDelay13: SUBS r1, r1, #1 BNE flagDelay13/* set refresh register for a big value(160 cycles) */ LDR r1, =0x22 STR r1, [r2, #DDRC_DYNAMIC_REFRESH - DDRC_BASE]/* Time delay 14. */ MOV r1, #0x100flagDelay14: SUBS r1, r1, #1 BNE flagDelay14/* Set SDRAM Initialisation Value to MODE */ LDR r1, =0xC083 STR r1, [r2, #DDRC_DYNAMIC_CONTROL - DDRC_BASE]/* Program the Mode registers */ LDR r5, =DDR_MODE_REGISTER2 LDR r0, [r5]/* Time delay 15. */ MOV r1, #0x100flagDelay15: SUBS r1, r1, #1 BNE flagDelay15/* Set SDRAM Initialisation Value to normal */ LDR r1, =0xC003 STR r1, [r2, #DDRC_DYNAMIC_CONTROL - DDRC_BASE]/* All of ddr-sdram initialize routine is over. */ LDR r2,=0x101e5200 LDR r1,=0x0 STR r1,[r2,#0]/* ----------------------------------------------------------------------------- *//* ----------------------------------------------------------------------------- *//* ----------------------------------------------------------------------------- *//* Initialize MEMC0 static bank 1 to enable flash's read and write. *//* ----------------------------------------------------------------------------- *//* ----------------------------------------------------------------------------- *//* ----------------------------------------------------------------------------- *///cutted by yuanyabin#if 1LDR r2, =MEMC_BASE//MOV r1, #0x80//16bit,modified by y48834//MOV r1, #0x81LDR r1,=FLASH_BIT_WIDTH STR r1, [r2, #MEMC_STATIC_CONFIG(1) - MEMC_BASE] //MOV r1, #0x3MOV r1, #0x2 STR r1, [r2, #MEMC_STATIC_WAITWEN(1) - MEMC_BASE]//MOV r1, #0x4MOV r1, #0x2 STR r1, [r2, #MEMC_STATIC_WAITOEN(1) - MEMC_BASE]//MOV r1, #0x18MOV r1, #0xc STR r1, [r2, #MEMC_STATIC_WAITRD(1) - MEMC_BASE]//MOV r1, #0x4MOV r1, #0x2 STR r1, [r2, #MEMC_STATIC_WAITPAGE(1) - MEMC_BASE]//MOV r1, #0xcMOV r1, #0x5 STR r1, [r2, #MEMC_STATIC_WAITWR(1) - MEMC_BASE]//MOV r1, #0xcMOV r1, #0x5 STR r1, [r2, #MEMC_STATIC_WAITTURN(1) - MEMC_BASE]MOV r1, #0x32 STR r1, [r2, #MEMC_AHB_TIMEOUT(0) - MEMC_BASE]#endif LDR r2,=0x101e5100 LDR r1,=0x0 STR r1,[r2,#0] mov pc, lr⌨️ 快捷键说明
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