lowlevel_init.s

华为 HI3510 BOOTLOADER HIBOOT 源码包

/*
 * (C) Copyright 2006, HISILICON Ltd.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <hisilicon/regs.h>

.globl lowlevel_init
lowlevel_init:
	/* check if I was running in ram */
	mov	r2, pc, lsr #24
	and	r2, r2, #0xF8
	cmp	r2, #0x60
	moveq	pc, lr
	cmp	r2, #0xF0
	moveq	pc, lr

	LDR     r2, =SYSTEM_CONTROL_BASE

/* Slow to normal configuration. */
	LDR     r1, =0x0fffbb40
	STR     r1, [r2, #0x14]

/*	LDR     r1, =0x11021202 */
	LDR     r1, =0x11820529
	STR     r1, [r2, #0x18]
	
	/* slow to normal */
	ldr	r1, [r2]
	orr     r1, #0x04
	str     r1, [r2]


/* ---------------------------------------------------------------------------------*/
/* ---------------------------------------------------------------------------------*/
/* ---------------------------------------------------------------------------------*/
/* Config the MEMC0 to a knowing state; For 32bit SDRAM is in MEMC's dynamic bank4. */
/* ---------------------------------------------------------------------------------*/
/* ---------------------------------------------------------------------------------*/
/* ---------------------------------------------------------------------------------*/

  
        LDR     r2, =MEMC_BASE 

/* Time delay 1. */
        LDR      r1, =0x4000
flagDelay1:  
        SUBS     r1, r1, #1
        BNE      flagDelay1


        MOV     r1, #0x1
        /*  Set enable bit */
        STR     r1, [r2, #MEMC_CONTROL - MEMC_BASE]
 
        
/* Set Clocking scheme */
/* ----------------------------------------------------------------------------- */
        LDR     r1, =0x112
        STR     r1, [r2, #MEMC_DYNAMIC_READCONFIG - MEMC_BASE]     


/* Set SDRAM Initialisation Value (I) to NOP (MEMCDynamicControl [8:7] to 2'b11) */
/* ----------------------------------------------------------------------------- */

        LDR     r1, =0xC183
        STR     r1, [r2 , #MEMC_DYNAMIC_CONTROL - MEMC_BASE]


/* Time delay 2. */
        LDR      r1, =0x4000
flagDelay2:  
        SUBS     r1, r1, #1
        BNE      flagDelay2



/* Set SDRAM Initialisation Value (I) to PALL (MEMCDynamicControl [8:7] to 2'b10) */
/* -----------------------------------------------------------------------------  */

        LDR     r1, =0xC103
        STR     r1, [r2 , #MEMC_DYNAMIC_CONTROL - MEMC_BASE]

/* NOP */
        LDR     r1, =0xC183
        STR     r1, [r2 , #MEMC_DYNAMIC_CONTROL - MEMC_BASE]



       
/* Write a small value (1) into the refresh register (MEMCDynamicRefresh) */
/*  ----------------------------------------------------------------------------- */

/* 0x1 (x16) = 16 cycles between refreshes */

        MOV     r1, #0x02
        STR     r1, [r2, #MEMC_DYNAMIC_REFRESH - MEMC_BASE]

/* NOP */
        LDR     r1, =0xC183
        STR     r1, [r2 , #MEMC_DYNAMIC_CONTROL - MEMC_BASE]



/* Perform refresh cycles */
/* ----------------------------------------------------------------------------- */

/* Time delay 3. */
        LDR      r1, =0x100
flagDelay3:  
        SUBS     r1, r1, #1
        BNE      flagDelay3
        



/* Write a small value (1) into the refresh register (MEMCDynamicRefresh) */
/*  ----------------------------------------------------------------------------- */

/* 0x1 (x16) = 16 cycles between refreshes */

        MOV     r1, #0x02
        STR     r1, [r2, #MEMC_DYNAMIC_REFRESH - MEMC_BASE]

/* NOP */
        LDR     r1, =0xC183
        STR     r1, [r2 , #MEMC_DYNAMIC_CONTROL - MEMC_BASE]



/* Perform refresh cycles */
/* ----------------------------------------------------------------------------- */

/* Time delay 31. */
        LDR      r1, =0x100
flagDelay31:  
        SUBS     r1, r1, #1
        BNE      flagDelay31

/* Write operational value into refresh reg (MEMCDynamicRefresh) */
/* ----------------------------------------------------------------------------- */

/* For 7.81us refresh rate, with 100MHz clock = (8 * 100)/16 = 0x22 */

        MOV     r1, #0x22
        STR     r1, [r2, #MEMC_DYNAMIC_REFRESH - MEMC_BASE]
        

/* NOP */
        LDR     r1, =0xC183
        STR     r1, [r2 , #MEMC_DYNAMIC_CONTROL - MEMC_BASE]



/* Time delay 4. */
        LDR      r1, =0x100
flagDelay4:  
        SUBS     r1, r1, #1
        BNE      flagDelay4



/* Program RAS/CAS latency (MEMCDynamicRASCAS[0,1,2,3]) */
/* ----------------------------------------------------------------------------- */

/* MEMCDynamicRASCASn [10:7] -> CAS latency in half cycle increments */
/* MEMCDynamicRASCASn  [3:0] -> RAS latency in one cycle increments */
/* 32'h0000 0202 => RAS = 2 cycles, CAS = 2 cycles */
/* 32'h0000 0182 => RAS = 2 cycles, CAS = 1.5 cycles */

        
        LDR     r1, =RAS_LATENCY         
       // LDR     r1, =0x203
        STR     r1, [r2 , #MEMC_DYNAMIC_RASCAS(0) - MEMC_BASE]

   

        
/* Write operational value into Config reg (MpmcDynamicConfig n) */
/* ----------------------------------------------------------------------------- */

/* For RBC : 32'h 0000 4880 */
/* For BRC : 32'h 0000 5880 */

/*        LDR     r1, =0x4880    */
        LDR     r1, =SDRAM_CONFIG_VALUE    
        STR     r1, [r2 , #MEMC_DYNAMIC_CONFIG(0) - MEMC_BASE]        
      
        
/* Set DynamicRP Register */
/* ----------------------------------------------------------------------------- */
       MOV     r1, #0x2
       STR     r1, [r2 , #MEMC_DYNAMIC_TRP - MEMC_BASE]

/* Set DynamicRAS Register */
/* ----------------------------------------------------------------------------- */
        //MOV     r1, #0x4
        MOV     r1, #0x04
        STR     r1, [r2 , #MEMC_DYNAMIC_TRAS - MEMC_BASE]

/* Set DynamicSREX Register */
/* ----------------------------------------------------------------------------- */
      // MOV     r1, #0x3
        MOV     r1, #0x7f
        STR     r1, [r2 , #MEMC_DYNAMIC_TSREX - MEMC_BASE]
       
        
/* Set DynamicWR Register */
/* ----------------------------------------------------------------------------- */
       // MOV     r1, #0x2
        MOV     r1, #0x02
        STR     r1, [r2 , #MEMC_DYNAMIC_TWR - MEMC_BASE]
/* Set DynamicRC Register */
/* ----------------------------------------------------------------------------- */
        MOV     r1, #0x06
        STR     r1, [r2 , #MEMC_DYNAMIC_TRC - MEMC_BASE]
/* Set DynamicRFC Register */
/* ----------------------------------------------------------------------------- */
        //MOV     r1, #0x2b
        MOV     r1, #0x07
        STR     r1, [r2 , #MEMC_DYNAMIC_TRFC - MEMC_BASE]
/* Set DynamicXSR Register */
/* ----------------------------------------------------------------------------- */
       // MOV     r1, #0x17
        MOV     r1, #0xff
        STR     r1, [r2 , #MEMC_DYNAMIC_TXSR - MEMC_BASE]

/* Set DynamicRRD Register */
/* ----------------------------------------------------------------------------- */
        //MOV     r1, #0x7
        MOV     r1, #0x02
        STR     r1, [r2 , #MEMC_DYNAMIC_TRRD - MEMC_BASE]

/* Set DynamicMRD Register */
/* ----------------------------------------------------------------------------- */
        //MOV     r1, #0x13
        MOV     r1, #0x02
        STR     r1, [r2 , #MEMC_DYNAMIC_TMRD - MEMC_BASE]

/* Set DynamicCDLR Register */
/* ----------------------------------------------------------------------------- */
       // MOV     r1, #0xe
        MOV     r1, #0x01
        STR     r1, [r2 , #MEMC_DYNAMIC_TCDLR - MEMC_BASE]
 



/* Set SDRAM Initialisation Value (I) to MODE (MEMCDynamicControl [8:7] to 2'b01) */
/* -----------------------------------------------------------------------------  */

        LDR     r1, =0xC083
        STR     r1, [r2 , #MEMC_DYNAMIC_CONTROL - MEMC_BASE]

/* Program the Mode Registers. SDRAM Addr[5] = 1'b1, all others 0 */
/* ----------------------------------------------------------------------------- */

/* SDRAM Addr[11:0] = 12'h020 */
/* For RBC : SDRAM Addr[11:0] translates to HADDR [25:13] = 0x40000 */
/* For BRC : SDRAM Addr[11:0] translates to HADDR [23:11] = 0x10000 */
/* To program the register, do a read from the memory base addr + the value above */

//        LDR     r5, =0x60080000
        LDR     r5, =SDRAM_MODE
        LDR     r0, [r5]
     


/* NOP */
        LDR     r1, =0xC183
        STR     r1, [r2 , #MEMC_DYNAMIC_CONTROL - MEMC_BASE]


/* Time delay 5. */
        LDR      r1, =0x4000
flagDelay5:  
        SUBS     r1, r1, #1
        BNE      flagDelay5





/* Set SDRAM Initialisation Value (I) to PALL */
/* ----------------------------------------------------------------------------- */

        LDR     r1, =0xC103
        STR     r1, [r2, #MEMC_DYNAMIC_CONTROL - MEMC_BASE]



/* NOP */
        LDR     r1, =0xC183
        STR     r1, [r2 , #MEMC_DYNAMIC_CONTROL - MEMC_BASE]