📄 regs.h

📁 华为 HI3510 BOOTLOADER HIBOOT 源码包
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#ifndef	__HISILICON_CHIP_REGISTERS_H__#define	__HISILICON_CHIP_REGISTERS_H__#define MEMC_BASE	0x10110000#define DDRC_BASE	0x10150000	#define SYSTEM_CONTROL_BASE	0x101E0000			/*	MEMC register description: */#define MEMC_CONTROL                 (MEMC_BASE)#define MEMC_STATUS                  (MEMC_BASE + 0x004)#define MEMC_CONFIG                  (MEMC_BASE + 0x008)#define MEMC_DYNAMIC_CONTROL         (MEMC_BASE + 0x020)#define MEMC_DYNAMIC_REFRESH         (MEMC_BASE + 0x024)#define MEMC_DYNAMIC_READCONFIG      (MEMC_BASE + 0x028)#define MEMC_DYNAMIC_TRP             (MEMC_BASE + 0x030)#define MEMC_DYNAMIC_TRAS            (MEMC_BASE + 0x034)#define MEMC_DYNAMIC_TSREX           (MEMC_BASE + 0x038)#define MEMC_DYNAMIC_TWR             (MEMC_BASE + 0x044)#define MEMC_DYNAMIC_TRC             (MEMC_BASE + 0x048)#define MEMC_DYNAMIC_TRFC            (MEMC_BASE + 0x04C)#define MEMC_DYNAMIC_TXSR            (MEMC_BASE + 0x050)#define MEMC_DYNAMIC_TRRD            (MEMC_BASE + 0x054)#define MEMC_DYNAMIC_TMRD            (MEMC_BASE + 0x058)#define MEMC_DYNAMIC_TCDLR           (MEMC_BASE + 0x05C)#define MEMC_STATIC_EXTENDEDWAIT     (MEMC_BASE + 0x080)/* Here x=0..3 .*/#define MEMC_DYNAMIC_CONFIG(x)       (MEMC_BASE + 0x100 + x * 0x20)#define MEMC_DYNAMIC_RASCAS(x)       (MEMC_BASE + 0x100 + x * 0x20 + 0x4)/* Here x=0..3 .*/#define MEMC_STATIC_CONFIG(x)        (MEMC_BASE + 0x200 + x * 0x20)#define MEMC_STATIC_WAITWEN(x)       (MEMC_BASE + 0x200 + x * 0x20 + 0x4)#define MEMC_STATIC_WAITOEN(x)       (MEMC_BASE + 0x200 + x * 0x20 + 0x8)#define MEMC_STATIC_WAITRD(x)        (MEMC_BASE + 0x200 + x * 0x20 + 0xC)#define MEMC_STATIC_WAITPAGE(x)      (MEMC_BASE + 0x200 + x * 0x20 + 0x10)#define MEMC_STATIC_WAITWR(x)        (MEMC_BASE + 0x200 + x * 0x20 + 0x14)#define MEMC_STATIC_WAITTURN(x)      (MEMC_BASE + 0x200 + x * 0x20 + 0x18)/* Here x=0..4 .*/#define MEMC_AHB_CONTROL(x)          (MEMC_BASE + 0x400 + x * 0x20)#define MEMC_AHB_STATUS(x)           (MEMC_BASE + 0x400 + x * 0x20 + 0x04)#define MEMC_AHB_TIMEOUT(x)          (MEMC_BASE + 0x400 + x * 0x20 + 0x08)/*	DDRC register description: */#define DDRC_CONTROL		     (DDRC_BASE)#define DDRC_DYNAMIC_CONTROL	     (DDRC_BASE + 0x020)/* Here x=0..3 .*/#define DDRC_DYNAMIC_CONFIG(x)       (DDRC_BASE + 0x100 + x * 0x20)#define DDRC_DYNAMIC_RASCAS(x)       (DDRC_BASE + 0x100 + x * 0x20 + 0x4)#define DDRC_DYNAMIC_REFRESH         (DDRC_BASE + 0x024)#define DDRC_DYNAMIC_READCONFIG      (DDRC_BASE + 0x028)#define DDRC_DYNAMIC_TRP             (DDRC_BASE + 0x030)#define DDRC_DYNAMIC_TRAS            (DDRC_BASE + 0x034)#define DDRC_DYNAMIC_TSREX           (DDRC_BASE + 0x038)#define DDRC_DYNAMIC_TWR             (DDRC_BASE + 0x044)#define DDRC_DYNAMIC_TRC             (DDRC_BASE + 0x048)#define DDRC_DYNAMIC_TRFC            (DDRC_BASE + 0x04C)#define DDRC_DYNAMIC_TXSR            (DDRC_BASE + 0x050)#define DDRC_DYNAMIC_TRRD            (DDRC_BASE + 0x054)#define DDRC_DYNAMIC_TMRD            (DDRC_BASE + 0x058)#define DDRC_DYNAMIC_TCDLR           (DDRC_BASE + 0x05C)/* watchdog */#define HISILICON_SCTL_BASE	0x101E0000	#define HIWDT_BASE      0x101E1000#define HIWDT_REG(x)	(HIWDT_BASE + (x))#define HIWDT_LOAD      0x000#define HIWDT_VALUE     0x004#define HIWDT_CTRL      0x008#define HIWDT_INTCLR    0x00C#define HIWDT_RIS       0x010#define HIWDT_MIS       0x014#define HIWDT_LOCK      0xC00#define HIWDT_UNLOCK_VAL        0x1ACCE551#endif /*End of __HI_BOARD_H__ */
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