hi_vda.c

华为 HI3510 BOOTLOADER HIBOOT 源码包

/******************************************************************************

  Copyright (C), 2001-2011, Hisilicon Tech. Co., Ltd.

 ******************************************************************************
  File Name     : hi_vda.c
  Version       : Initial Draft
  Author        : Hisilicon multimedia software group
  Created       : 2004/08/06
  Last Modified :
  Description   : Provides all VDA drivers.
  Function List :
                  readReg
                  Vda_Adv7170_command
                  Vda_Adv7171_Init
                  writeReg
                  writeRegs
  History       :
  1.Date        : 2004/08/06
    Author      : yuanyabin
    Modification: Created file

******************************************************************************/

#include <config.h>

#if defined(CONFIG_HI3510_LOGO)


#include "hi_common/hi.h"

#include "hi_inc.h"
#include "hi_i2c.h"

#include "hi_video.h"
#include "hi_vda.h"

#define I2C_ADV7171     0x56 

#define ADV7171_NUM_REGISTERS   128


struct adv7171 {
	
     /* struct i2c_client *client; */
    int addr;
	
	UINT8 reg[ADV7171_NUM_REGISTERS];

	int norm;	
	int master;	
	int ccir;
	
	int input;
	int enable;
	int bright;
	int contrast;
	int hue;
	int sat;
};



//static char *inputs[] = { "pass_through", "play_back" };
//static char *norms[] = { "PAL", "NTSC" };
//static char *master[] = {"slaver", "master"};
//static char *ccir[] = {"ccir656", "ccir601"};


/* ----------------------------------------------------------------------- */
// Output filter:  S-Video  Composite

#define MR050       0x11	//0x09
#define MR060       0x14	//0x0c

//---------------------------------------------------------------------------
#define TR0MODE_656  0x08  //added by yuanyabin 05/1/27
#define TR0MODE_601  0x04  //modified by yuanyabin 05/1/27


#define TR0RST      0x80

#define TR1CAPT	    0x00
#define TR1PLAY	    0x00


static const UINT8 init_656_NTSC[] = {
	0x00, 0xb4,		// MR0
	0x01, 0x00,		// MR1
	0x02, 0x00,		// MR2 RTC control: bits 2 and 1 
	0x03, 0x00,		// MR3
	0x04, 0x15,		// MR4
	0x05, 0x00,		// Reserved
	0x06, 0x00,		// Reserved
	0x07, TR0MODE_656,	// TM0
	0x08, TR1CAPT,		// TM1
	0x09, 0x16,		// Fsc0
	0x0a, 0x7c,		// Fsc1
	0x0b, 0xf0,		// Fsc2
	0x0c, 0x21,		// Fsc3
	0x0d, 0x00,		// Subcarrier Phase
	0x0e, 0x00,		// Closed Capt. Ext 0
	0x0f, 0x00,		// Closed Capt. Ext 1
	0x10, 0x00,		// Closed Capt. 0
	0x11, 0x00,		// Closed Capt. 1
	0x12, 0x00,		// Pedestal Ctl 0
	0x13, 0x00,		// Pedestal Ctl 1
	0x14, 0x00,		// Pedestal Ctl 2
	0x15, 0x00,		// Pedestal Ctl 3
	0x16, 0x00,		// CGMS_WSS_0
	0x17, 0x00,		// CGMS_WSS_1
	0x18, 0x00,		// CGMS_WSS_2
	0x19, 0x00,		// Teletext Ctl 
};


static const UINT8 init_656_PAL[] = {

	0x00, 0xb5,		// MR0, CIF, PAL BDGHI
	0x01, 0x00,		// MR1, 
	0x02, 0x00,		// MR2 RTC control: bits 2 and 1,
	0x03, 0x00,		// MR3
	0x04, 0x15,		// MR4, RGB OUTPUT
	0x05, 0x00,		// Reserved
	0x06, 0x00,		// Reserved
	0x07, TR0MODE_656,	// TM0
	0x08, TR1CAPT,		// TM1
	0x09, 0xcb,		// Fsc0
	0x0a, 0x8a,		// Fsc1
	0x0b, 0x09,		// Fsc2
	0x0c, 0x2a,		// Fsc3
	0x0d, 0x00,		// Subcarrier Phase
	0x0e, 0x00,		// Closed Capt. Ext 0
	0x0f, 0x00,		// Closed Capt. Ext 1
	0x10, 0x00,		// Closed Capt. 0
	0x11, 0x00,		// Closed Capt. 1
	0x12, 0x00,		// Pedestal Ctl 0
	0x13, 0x00,		// Pedestal Ctl 1
	0x14, 0x00,		// Pedestal Ctl 2
	0x15, 0x00,		// Pedestal Ctl 3
	0x16, 0x00,		// CGMS_WSS_0
	0x17, 0x00,		// CGMS_WSS_1
	0x18, 0x00,		// CGMS_WSS_2
	0x19, 0x00,		// Teletext Ctl     	
};




static  UINT8 init_601_NTSC[] = {
	0x00, 0xb4,		// MR0
	0x01, 0x00,  		// MR1
	0x02, 0x08,  //0x00,		// MR2 RTC control: bits 2 and 1 
	0x03, 0x04,  //0x00,		// MR3
	0x04, 0x0C,  //0x15,		// MR4
	0x05, 0x00,		// Reserved
	0x06, 0x00,		// Reserved
	0x07, TR0MODE_601,		// TM0
	0x08, TR1CAPT,		// TM1
	0x09, 0x16,		// Fsc0
	0x0a, 0x7c,		// Fsc1
	0x0b, 0xf0,		// Fsc2
	0x0c, 0x21,		// Fsc3
	0x0d, 0x00,		// Subcarrier Phase
	0x0e, 0x00,		// Closed Capt. Ext 0
	0x0f, 0x00,		// Closed Capt. Ext 1
	0x10, 0x00,		// Closed Capt. 0
	0x11, 0x00,		// Closed Capt. 1
	0x12, 0x00,		// Pedestal Ctl 0
	0x13, 0x00,		// Pedestal Ctl 1
	0x14, 0x00,		// Pedestal Ctl 2
	0x15, 0x00,		// Pedestal Ctl 3
	0x16, 0x00,		// CGMS_WSS_0
	0x17, 0x00,		// CGMS_WSS_1
	0x18, 0x00,		// CGMS_WSS_2
	0x19, 0x00,		// Teletext Ctl 
};



static  UINT8 init_601_PAL[] = {
	


	0x00, 0xb5,		// MR0, CIF, PAL BDGHI
	0x01, 0x00,		// MR1, 
	0x02, 0x08,  //0x00,		// MR2 RTC control: bits 2 and 1,
	0x03, 0x04,  //0x00,		// MR3
	0x04, 0x1C,  //0x15,		// MR4, RGB OUTPUT
	0x05, 0x00,		// Reserved
	0x06, 0x00,		// Reserved
	0x07, TR0MODE_601,	// TM0
	0x08, TR1CAPT,		// TM1
	0x09, 0xcb,		// Fsc0
	0x0a, 0x8a,		// Fsc1
	0x0b, 0x09,		// Fsc2
	0x0c, 0x2a,		// Fsc3
	0x0d, 0x00,		// Subcarrier Phase
	0x0e, 0x00,		// Closed Capt. Ext 0
	0x0f, 0x00,		// Closed Capt. Ext 1
	0x10, 0x00,		// Closed Capt. 0
	0x11, 0x00,		// Closed Capt. 1
	0x12, 0x00,		// Pedestal Ctl 0
	0x13, 0x00,		// Pedestal Ctl 1
	0x14, 0x00,		// Pedestal Ctl 2
	0x15, 0x00,		// Pedestal Ctl 3
	0x16, 0x00,		// CGMS_WSS_0
	0x17, 0x00,		// CGMS_WSS_1
	0x18, 0x00,		// CGMS_WSS_2
	0x19, 0x00,		// Teletext Ctl     	
};



static struct i2c_client client_template = {
        "ADV7171",
        0,
        0,
        I2C_ADV7171,      
        NULL
};


static int adv7171_i2c_id = 0;


/***********************************************************************************/
static HI_RET writeReg(IO struct i2c_client *pstClient, IN UINT8 u8Reg, IN UINT8 u8Data)
{
	struct adv7171 *dev = (struct adv7171 *)(pstClient->data);

	dev->reg[u8Reg] = u8Data;

    I2C_Write(pstClient, u8Reg, u8Data);
        
    return HI_OK;
}


/***********************************************************************************/
static HI_RET writeRegs(IO struct i2c_client *pstClient, IN UINT8 *pu8Data, IN UINT32 u32Len)
{
	struct adv7171 *dev = (struct adv7171 *)(pstClient->data);
	int i = 0;
              
    	while (i < u32Len) 
    	{
        	I2C_Write(pstClient, pu8Data[i], pu8Data[i+1]);     
    		dev->reg[i] = pu8Data[i+1];
        	i += 2;
	}	
	return HI_OK;
}


/***********************************************************************************/
static UINT8 readReg(IN struct i2c_client *pstClient, IN UINT8 u8Reg)
{
    return I2C_Read(pstClient, u8Reg);
}



/********************************************************************
int VDA_Init(IN INT32 s32Ccir, IN INT32 s32Norm, IN INT32 s32Master)
       
output: err  HI_OK.
        err HI_ERROR.                                 

s32Ccir: 
#define VIDEO_MODE_CCIR656	0
#define VIDEO_MODE_CCIR601	1

s32Norm:
#define VIDEO_NORM_PAL		0
#define VIDEO_NORM_NTSC		1
#define VIDEO_NORM_SECAM	2
#define VIDEO_NORM_AUTO		3

s32Master:
#define VIDEO_NORM_MASTER	1
#define VIDEO_NORM_SLAVER	0


********************************************************************/

static struct i2c_client *client = NULL;
static struct i2c_client vadClient;

HI_RET VDA_Init(IN INT32 s32Ccir, IN INT32 s32Norm, IN INT32 s32Master)
{
	int i;
	HI_RET err = HI_OK;
	struct adv7171 *encoder;
	int Arg;
	
	//printf("adv7171.c: detecting adv7171 client...\n");

#if 1
	client = &vadClient;
#else
	if(client == NULL)
	{
		client = &vadClient;
	}
	else
	{
		printf("vda has been intialized.\n");
		printf("Use command to set.\n");
		if(s32Ccir == VIDEO_MODE_CCIR656)
		{
			if(s32Norm == VIDEO_NORM_PAL)
			{
				Arg = VIDEO_MODE_656_PAL;
				VDA_Command(ENCODER_SET_NORM, &Arg);
				return(HI_OK);
			}
				
			else if(s32Norm == VIDEO_NORM_NTSC)
			{
				Arg = VIDEO_MODE_656_NTSC;
				VDA_Command(ENCODER_SET_NORM, &Arg);
				return(HI_OK);
			}
			else
			{
				err = HI_ERROR;
            			goto err_out;
            		}
		}
		else if(s32Ccir == VIDEO_MODE_CCIR601)
		{
			if(s32Norm == VIDEO_NORM_PAL)
			{
				if(s32Master == VIDEO_MODE_MASTER)
				{
					Arg = VIDEO_MODE_601_PAL_MASTER;
					VDA_Command(ENCODER_SET_NORM, &Arg);
					return(HI_OK);
				}
				else if(s32Master == VIDEO_MODE_SLAVER)
				{
					Arg = VIDEO_MODE_601_PAL_SLAVER;
					VDA_Command(ENCODER_SET_NORM, &Arg);
					return(HI_OK);
				}
				else