hi_intrctl.h

华为 HI3510 BOOTLOADER HIBOOT 源码包

/* ambaIntrCtl.h - amba(ARM9) interrupt controller driver header file */

/* Copyright 2002-2003 HUAWEI TECHNOLOGIES CO., LTD. */


#define AMBA_INT_NUM_LEVELS 32
#define AMBA_INT_LVL_MASK 0xffffffff

#define ECS_INT_NUM_LEVELS AMBA_INT_NUM_LEVELS
#define ECS_INT_LVL_MASK   AMBA_INT_LVL_MASK


#if defined(BOARD_HI3510FPGA)

/* 
 * definitions for the interrupt levels:
*/
	#define INT_LVL_PHY	31
	#define INT_LVL_SF	30
	#define INT_LVL_ZSPINT1	29
	#define INT_LVL_ZSPINT0	28
	#define INT_LVL_ZSP2ARM	27
	#define INT_LVL_DEBLK	26
	#define INT_LVL_SIO	25
	#define INT_LVL_DSU	24
	#define INT_LVL_VIU	23
	#define INT_LVL_GPIO7	22
	#define INT_LVL_GPIO6	21
	#define INT_LVL_GPIO5	20
	#define INT_LVL_GPIO4	19
	#define INT_LVL_RESERVED0	18
	#define INT_LVL_DMA	17
	#define INT_LVL_VOU	16
	#define INT_LVL_USB	15
	#define INT_LVL_I2C	14
	#define INT_LVL_SERIAL_1	13
	#define INT_LVL_SERIAL_0	12
	#define INT_LVL_SSP	11
	#define INT_LVL_RTC	10
	#define INT_LVL_GPIO_3	9
	#define INT_LVL_GPIO_2	8
	#define INT_LVL_GPIO_1	7
	#define INT_LVL_GPIO_0	6
	#define INT_LVL_TIMER_2	5
	#define INT_LVL_TIMER_1	4
	#define INT_LVL_COMMTX	3
	#define INT_LVL_COMMRX	2
	#define INT_LVL_PROGRAMMABLE	1
	#define INT_LVL_WATCHDOG	0

/*
 * definitions for interrupt vectors:
*/

	#define INT_VEC_PHY	31
	#define INT_VEC_SF	30
	#define INT_VEC_ZSPINT1	29
	#define INT_VEC_ZSPINT0	28
	#define INT_VEC_ZSP2ARM	27
	#define INT_VEC_DEBLK	26
	#define INT_VEC_SIO	25
	#define INT_VEC_DSU	24
	#define INT_VEC_VIU	23
	#define INT_VEC_GPIO7	22
	#define INT_VEC_GPIO6	21
	#define INT_VEC_GPIO5	20
	#define INT_VEC_GPIO4	19
	#define INT_VEC_RESERVED0	18
	#define INT_VEC_DMA	17
	#define INT_VEC_VOU	16
	#define INT_VEC_USB	15
	#define INT_VEC_I2C	14
	#define INT_VEC_SERIAL_1	13
	#define INT_VEC_SERIAL_0	12
	#define INT_VEC_SSP	11
	#define INT_VEC_RTC	10
	#define INT_VEC_GPIO_3	9
	#define INT_VEC_GPIO_2	8
	#define INT_VEC_GPIO_1	7
	#define INT_VEC_GPIO_0	6
	#define INT_VEC_TIMER_2	5
	#define INT_VEC_TIMER_1	4
	#define INT_VEC_COMMTX	3
	#define INT_VEC_COMMRX	2
	#define INT_VEC_PROGRAMMABLE	1
	#define INT_VEC_WATCHDOG	0
#endif	



#if defined(BOARD_HI3510DEMO)

/* 
 * definitions for the interrupt levels:
*/
	#define INT_LVL_PHY	31
	#define INT_LVL_SF	30
	#define INT_LVL_ZSPINT1	29
	#define INT_LVL_ZSPINT0	28
	#define INT_LVL_ZSP2ARM	27
	#define INT_LVL_DEBLK	26
	#define INT_LVL_SIO	25
	#define INT_LVL_DSU	24
	#define INT_LVL_VIU	23
	#define INT_LVL_GPIO7	22
	#define INT_LVL_GPIO6	21
	#define INT_LVL_GPIO5	20
	#define INT_LVL_GPIO4	19
	#define INT_LVL_RESERVED0	18
	#define INT_LVL_DMA	17
	#define INT_LVL_VOU	16
	#define INT_LVL_USB	15
	#define INT_LVL_I2C	14
	#define INT_LVL_SERIAL_1	12
	#define INT_LVL_SERIAL_0	13
	#define INT_LVL_SSP	11
	#define INT_LVL_RTC	10
	#define INT_LVL_GPIO_3	9
	#define INT_LVL_GPIO_2	8
	#define INT_LVL_GPIO_1	7
	#define INT_LVL_GPIO_0	6
	#define INT_LVL_TIMER_2	5
	#define INT_LVL_TIMER_1	4
	#define INT_LVL_COMMTX	3
	#define INT_LVL_COMMRX	2
	#define INT_LVL_PROGRAMMABLE	1
	#define INT_LVL_WATCHDOG	0

/*
 * definitions for interrupt vectors:
*/

	#define INT_VEC_PHY	31
	#define INT_VEC_SF	30
	#define INT_VEC_ZSPINT1	29
	#define INT_VEC_ZSPINT0	28
	#define INT_VEC_ZSP2ARM	27
	#define INT_VEC_DEBLK	26
	#define INT_VEC_SIO	25
	#define INT_VEC_DSU	24
	#define INT_VEC_VIU	23
	#define INT_VEC_GPIO7	22
	#define INT_VEC_GPIO6	21
	#define INT_VEC_GPIO5	20
	#define INT_VEC_GPIO4	19
	#define INT_VEC_RESERVED0	18
	#define INT_VEC_DMA	17
	#define INT_VEC_VOU	16
	#define INT_VEC_USB	15
	#define INT_VEC_I2C	14
	#define INT_VEC_SERIAL_1	12
	#define INT_VEC_SERIAL_0	13
	#define INT_VEC_SSP	11
	#define INT_VEC_RTC	10
	#define INT_VEC_GPIO_3	9
	#define INT_VEC_GPIO_2	8
	#define INT_VEC_GPIO_1	7
	#define INT_VEC_GPIO_0	6
	#define INT_VEC_TIMER_2	5
	#define INT_VEC_TIMER_1	4
	#define INT_VEC_COMMTX	3
	#define INT_VEC_COMMRX	2
	#define INT_VEC_PROGRAMMABLE	1
	#define INT_VEC_WATCHDOG	0

#endif







#if defined(BOARD_HI3517FPGA)||(BOARD_HI3517DEMO)
/* 
 * definitions for the interrupt levels:
*/
	#define INT_LVL_PHY	31
	#define INT_LVL_RESERVED14	30
	#define INT_LVL_RESERVED13	29
	#define INT_LVL_SF	28
	#define INT_LVL_SIO	27
	#define INT_LVL_RESERVED12	26
	#define INT_LVL_RESERVED11	25
	#define INT_LVL_RESERVED10	24
	#define INT_LVL_RESERVED9	23
	#define INT_LVL_RESERVED8	22
	#define INT_LVL_RESERVED7	21
	#define INT_LVL_RESERVED6	20
	#define INT_LVL_RESERVED5	19
	#define INT_LVL_ZSP2ARM	18
	#define INT_LVL_DMA	17
	#define INT_LVL_RESERVED4	16
	#define INT_LVL_RESERVED3	15
	#define INT_LVL_RESERVED2	14
	#define INT_LVL_RESERVED1	13
	#define INT_LVL_SERIAL_0	12
	#define INT_LVL_SSP	11
	#define INT_LVL_RTC	10
	#define INT_LVL_RESERVED0	9
	#define INT_LVL_GPIO_2	8
	#define INT_LVL_GPIO_1	7
	#define INT_LVL_GPIO_0	6
	#define INT_LVL_TIMER_2	5
	#define INT_LVL_TIMER_1	4
	#define INT_LVL_COMMTX	3
	#define INT_LVL_COMMRX	2
	#define INT_LVL_PROGRAMMABLE	1
	#define INT_LVL_WATCHDOG	0

/*
 * definitions for interrupt vectors:
*/
	#define INT_VEC_PHY	31
	#define INT_VEC_RESERVED14	30
	#define INT_VEC_RESERVED13	29
	#define INT_VEC_SF	28
	#define INT_VEC_SIO	27
	#define INT_VEC_RESERVED12	26
	#define INT_VEC_RESERVED11	25
	#define INT_VEC_RESERVED10	24
	#define INT_VEC_RESERVED9	23
	#define INT_VEC_RESERVED8	22
	#define INT_VEC_RESERVED7	21
	#define INT_VEC_RESERVED6	20
	#define INT_VEC_RESERVED5	19
	#define INT_VEC_ZSP2ARM	18
	#define INT_VEC_DMA	17
	#define INT_VEC_RESERVED4	16
	#define INT_VEC_RESERVED3	15
	#define INT_VEC_RESERVED2	14
	#define INT_VEC_RESERVED1	13
	#define INT_VEC_SERIAL_0	12
	#define INT_VEC_SSP	11
	#define INT_VEC_RTC	10
	#define INT_VEC_RESERVED0	9
	#define INT_VEC_GPIO_2	8
	#define INT_VEC_GPIO_1	7
	#define INT_VEC_GPIO_0	6
	#define INT_VEC_TIMER_2	5
	#define INT_VEC_TIMER_1	4
	#define INT_VEC_COMMTX	3
	#define INT_VEC_COMMRX	2
	#define INT_VEC_PROGRAMMABLE	1
	#define INT_VEC_WATCHDOG	0
#endif

#if defined(BOARD_HI3560FPGA)||(BOARD_HI3560DEMO)
/* 
 * definitions for the interrupt levels:
*/
	#define INT_LVL_PHY			31
	#define INT_LVL_RESERVED4		30
	#define INT_LVL_SPDIF			29
	#define INT_LVL_SF			28
	#define INT_LVL_SIO			27
	#define INT_LVL_DSU			26
	#define INT_LVL_VIU                     25
	#define INT_LVL_RESERVED3		24
	#define INT_LVL_RESERVED2		23
	#define INT_LVL_ATAH			22
	#define INT_LVL_NANDC			21
	#define INT_LVL_USB	                20
	#define INT_LVL_I2C                     19
	#define INT_LVL_ZSP2ARM                 18
	#define INT_LVL_DMA                     17
	#define INT_LVL_VOU                     16
	#define INT_LVL_SCI                     15
	#define INT_LVL_RESERVED1		14
	#define INT_LVL_SERIAL_1		13
	#define INT_LVL_SERIAL_0		12
	#define INT_LVL_SSP			11
	#define INT_LVL_RTC			10
	#define INT_LVL_RESERVED0		9
	#define INT_LVL_GPIO_2			8
	#define INT_LVL_GPIO_1			7
	#define INT_LVL_GPIO_0			6
	#define INT_LVL_TIMER_2			5
	#define INT_LVL_TIMER_1			4
	#define INT_LVL_COMMTX			3
	#define INT_LVL_COMMRX			2
	#define INT_LVL_PROGRAMMABLE	        1
	#define INT_LVL_WATCHDOG 		0

/*
 * definitions for interrupt vectors:
*/
	#define INT_VEC_PHY			31
	#define INT_VEC_RESERVED4		30
	#define INT_VEC_SPDIF			29
	#define INT_VEC_SF			28
	#define INT_VEC_SIO			27
	#define INT_VEC_DSU			26
	#define INT_VEC_VIU                     25
	#define INT_VEC_RESERVED3		24
	#define INT_VEC_RESERVED2		23
	#define INT_VEC_ATAH			22
	#define INT_VEC_NANDC			21
	#define INT_VEC_USB	                20
	#define INT_VEC_I2C                     19
	#define INT_VEC_ZSP2ARM                 18
	#define INT_VEC_DMA                     17
	#define INT_VEC_VOU                     16
	#define INT_VEC_SCI                     15
	#define INT_VEC_RESERVED1		14
	#define INT_VEC_SERIAL_1		13
	#define INT_VEC_SERIAL_0		12
	#define INT_VEC_SSP			11
	#define INT_VEC_RTC			10
	#define INT_VEC_RESERVED0		9
	#define INT_VEC_GPIO_2			8
	#define INT_VEC_GPIO_1			7
	#define INT_VEC_GPIO_0			6
	#define INT_VEC_TIMER_2			5
	#define INT_VEC_TIMER_1			4
	#define INT_VEC_COMMTX			3
	#define INT_VEC_COMMRX			2
	#define INT_VEC_PROGRAMMABLE	        1
	#define INT_VEC_WATCHDOG 		0
#endif